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Your search keyword '"Hu, Chenming"' showing total 34 results
Start Over Author "Hu, Chenming" Journal solid-state electronics
34 results on '"Hu, Chenming"'

32. A versatile compact model of resistive random-access memory (RRAM).

Author

Tung, Chien-Ting, Kumar Dabhi, Chetan, Salahuddin, Sayeef, and Hu, Chenming

Abstract

• A RRAM compact model compatible with OxRAM and CBRAM. • Accurately model experimental DC and transient data of various RRAM structures. • RRAM variation and disturb effect are modeled. • Compatible with SPICE simulation and memory circuit designs. We present a versatile compact model for resistive random-access memory (RRAM) that can model different types of RRAM devices such as oxide-RRAM (OxRAM) and conducting-bridge-RRAM (CBRAM). The model unifies the switching mechanisms of these RRAMs into a single framework. We showcase the model's accuracy in reproducing published experimental device DC and transient characteristics of various RRAM structures. We also demonstrate the model's efficacy in capturing RRAM variability and conducting 1T1R circuit simulations. [ABSTRACT FROM AUTHOR]

Published
2024
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33. Deep learning-based I-V Global Parameter Extraction for BSIM-CMG.

Author

Chavez, Fredo, Tung, Chien-Ting, Kao, Ming-Yen, Hu, Chenming, Chen, Jen-Hao, and Khandelwal, Sourabh

Subjects
*DEEP learning, *MONTE Carlo method, *THRESHOLD voltage, *FIELD-effect transistors
Abstract

A new deep-learning-based parameter extraction for a global (multiple gate lengths) BSIM-CMG drain-current model is presented in this paper. The approach starts with generating 300K training dataset, consisting of 778 million data points to train the deep learning engine. Training data is generated by Monte Carlo simulation. The I-V data and the device geometry information from multiple devices serve to train a deep-learning (DL) model to predict BSIM-CMG parameters. The performance of DL-based extraction is verified by using the trained DL model to extract parameters of 10 nm FinFET technology simulated with TCAD. The DL-extracted BSIM-CMG model shows a good accuracy for eight different gate-lengths. The created BSIM-CMG global model was also able to reproduce the scalability in key electrical performance parameters such as off current I o f f , saturation current I s a t , linear current I l i n and the threshold voltage in linear V t h , l i n and saturation V t h , s a t conditions. The developed solution significantly reduces the model extraction time for a global BSIM-CMG model. This new technique can expedite the development of process design kits (PDK). • Automatic parameter extraction of BSIM-CMG I-V global parameters. • Tested on TCAD simulated data calibrated to Intel 10 nm node with gate lengths from 16 nm to 100 nm. • Created global model captures the trends in I-V data and key electrical parameters accurately. [ABSTRACT FROM AUTHOR]

Published
2023
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34. Highly scaled (L g ∼56nm) gate-last Si tunnel field-effect transistors with I ON >100μA/μm

Author

Loh, Wei-Yip, Jeon, Kanghoon, Kang, Chang Yong, Oh, Jungwoo, King Liu, Tsu-Jae, Tseng, Hsing-Huang, Xiong, Wade, Majhi, Prashant, Jammy, Raj, and Hu, Chenming

Subjects
*SILICON-on-insulator technology, *FIELD-effect transistors, *TUNNELS, *COMPLEMENTARY metal oxide semiconductors, *SIMULATION methods & models, *ELECTRIC resistance, *TEMPERATURE effect, *NONLINEAR theories
Abstract

Abstract: Planar band-to-band tunneling FETs (TFETs) have been fabricated on silicon-on-insulator (SOI) substrates using conventional CMOS technologies with a highly scaled sub-60nm gate length (effective gate length [L g]∼40nm due to an overlap between the source and gate) and different anneal sequences. The optimal anneal sequence including spike and flash annealing resulted in a drive ON current (I ON))>100μA/μm with I ON/IOFF >105 at a drain bias of −1V. The devices exhibited negative differential resistance and non-linear subthreshold temperature dependencies, consistent with the band-to-band tunneling mechanism. Simulations using a 2-D TCAD simulator, MEDICI, agreed with experimental data, demonstrating the possibility of Si tunnel transistors in logic applications. [Copyright &y& Elsevier]

Published
2011
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