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This study reports on the electrical characteristics of (1 1 0)-oriented nMOSFETs with a direct contact La-silicate/Si interface structure and the detailed comparison with (1 0 0)-oriented nMOSFETs. Precise control of oxygen partial pressure can provide the scaled EOT down to 0.73 nm on (1 1 0) orientation in common with (1 0 0) orientation. No frequency dispersion in Cgc–V characteristic for (1 1 0)-oriented nMOSFETs is successfully demonstrated at scaled EOT region, while higher amount of available bonds on (1 1 0) surface results in a larger interface state density, leading to the degradation of sub-threshold slope. High breakdown voltages of 2.85 V and 2.9 V for (1 0 0)- and (1 1 0)-oriented nMOSFETs are considered to be due to superior interfacial property. The electron mobility on (1 1 0) orientation is lower than that on (1 0 0) orientation because of the smaller energy split between fourfold valleys and twofold valleys as well as the larger density of states for lower-energy valleys in the (1 1 0) surface. Moreover, electron mobility is reduced with decreasing EOT in both (1 0 0)- and (1 1 0)-oriented nMOSFETs. It is found that threshold voltage instability by positive bias stress is mainly responsible for bulk trapping of electron even with a larger interface state density in (1 1 0) orientation and influence of surface orientation on threshold voltage instability is negligibly small.

This study focuses on studying the effective electron mobility in direct contact La-silicate/Si structure based nMOSFETs and searching for the difference of the mobility characteristics compared with the SiO 2 MOSFETs. In this study, three types of gate electrode structure were prepared to investigate the mobility characteristics over a wide EOT range; W for EOT of 1.63 nm, TiN/W for EOT of 1.02 nm and metal-inserted poly-Si (MIPS) for EOT of 0.71 nm. Since the silicate formation is basically caused by the presence of oxygen, Si layer in MIPS can suppress the oxygen in-diffusion from atmosphere, resulting in scaled EOT. It is found that the E eff dependence of mobility with La-silicate is observed to differ from the mobility of SiO 2 MOSFETs. The electron mobility with La-silicate shows the weaker E eff dependence than the mobility of SiO 2 nMOSFETs in middle and high E eff region. This suggests an existence of additional mobility component related to the direct contact La-silicate/Si structure. The effective electron mobility is degraded with decreasing EOT in entire E eff region. This means that the scattering sources including Coulomb scattering, phonon scattering and surface roughness scattering are located not at La-silicate/Si interface but the inside of gate stacks and approach the Si inversion channel. Coulomb scattering and phonon scattering are thought to be strengthened by increasing k -value because of the enhancement of Coulomb scattering potential and higher ionicity in La-silicate gate dielectrics. The influence of metal/high- k interface is also considered to affect on the mobility with decreasing the EOT.

Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48 nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μeff) has been observed. A high μeff of 300 cm2/V s with relatively low interfacial state density (Dit) of 1011 cm−2/eV can be achieved when annealed at 500 °C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2 nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in Dit and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation.

Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage (VFB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the VFB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive VFB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA.