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Abstract This work is an extension of our previous work where the major focus was to understand the device physics and optimize its performance. In this extended work, we intend to investigate the applicability of Dielectric pocket (DP) based TFETs for low power applications. For that, firstly the device architecture is well optimized by imposing several gate and dielectric engineering techniques and thereafter the well optimized architecture is verified for analog, digital and wireless applications. Different TFET based device architectures have been examined using ATLAS simulation software. The key points citing each of the device architectures i.e. DP Hetero-Dielectric (H-D) TFET, DP Dual Material Gate (DMG) TFET and DP Dual Material Gate Hetero-Dielectric (DMG H-D) TFET with their merits and limitations for the future applications have been explained. During the analysis, it was found that DP H-D TFET outperforms other two cases and hence it has been further examined for analog applications using g m1 /I ds (transconductance versus drain current) factor. For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. Further, for wireless applications device linearity and distortion governing parameters have been analyzed. It was concluded that DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications. Highlights • DP TFET architecture is well optimized by imposing several gate and dielectric engineering techniques. • The merits and limitations of DP H-D TFET, DP DMG TFET and DP DMG H-D TFET for the future applications have been explained. • For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. • For wireless applications device linearity and distortion governing parameters have been analyzed. • DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications. [ABSTRACT FROM AUTHOR]

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation. [ABSTRACT FROM AUTHOR]

In this paper, drain current model has been formulated for Double Gate (DG) p-n-i-n Tunnel FET (TFET) using Lambert-W function. The model includes the impact of mobile charges, gate dielectric thickness (t ox ) and channel thickness (t si ) on quasi fermi level, gate threshold voltage (V TG ), onset voltage (V Gonset ) and Tunneling Barrier Width (TBW) over the entire operating range i.e. accumulation to inversion state. Important electrostatic and electrical parameters such as the effective potential (φ effective ) at the center of the channel, 2-D channel potential, electric field, energy band profile and Tunneling Barrier Width (TBW) dependent drain current have been modeled. Moreover, gate and drain bias controllability in different operating regimes has also been investigated by varying oxide thickness (t ox ), channel thickness (t si ), intrinsic channel length (L int ) and at different temperatures. Important FOMs required for analog circuit performance such as transconductance (g m ), drain conductance (g d ), output resistance (R out ), early voltage (V EA ) have also been evaluated and verified using ATLAS device simulation software. [ABSTRACT FROM AUTHOR]

The performance of conventional Tunnel FETs struggling from ambipolar issues, insufficient on-current, lower transconductance value, higher delay and lower cut off frequency has been improved by introducing several material and device engineering concepts in past few years. Keeping this in view, another interesting and reliable option i.e. Dielectric Pocket TFET (featuring a dielectric pocket placement near tunneling junction) has been comprehensively and qualitatively demonstrated using ATLAS device simulator. The architecture has been explored in terms of various device electrostatic parameters such as potential, energy band profile, electron and hole concentration, electric field variation and band to band generation rate (G BTB ) near the tunneling junction where the Dielectric Pocket (DP) has been introduced. Subsequently, a detailed investigation by changing the position and dielectric constant of pocket at respective junctions has been made where DP induced variations in drain current, transconductance and parasitic capacitance have been examined. The work highlights major improvements over conventional TFET in terms of lower subthreshold swing and threshold voltage, higher drain current and transconductance, improved on-to-off current ratio, suppressed ambipolar conduction and improved dynamic power dissipation issues for low voltage analog and digital applications. [ABSTRACT FROM AUTHOR]

The present work demonstrates the investigation of T-shaped Double Gate MOSFET for analog and digital performance. The 2D analytical modeling scheme is presented using Evanescent Mode Analysis (EMA). The applicability of the proposed model has been verified using ATLAS 3D device simulation. The device exploits peaks in the electric field inside the channel (due to T-shaped gate) for better carrier transport efficiency and subsequently higher drain current and trans-conductance. The impact of dielectric constant of the void layer (due to T-shaped gate) on the electrostatic of the device has been investigated using basic electrical parameters such as: sub-threshold slope, Drain Induced Barrier Lowering DIBL, device gain and I on /I off ratio. The comparative study between T-shaped DG with the conventional DG MOSFET is also presented. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (V th ). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model for Junctionless (JL) Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) based biosensor for label free electrical detection of biomolecules like enzyme, cell, DNA etc. using the Dielectric Modulation (DM) technique has been developed. The analytical results are validated with the help of “Sentaurus” device simulation software. For the biomolecule immobilization, nanogap cavity is formed in the JL MOSFET by etching gate oxide layer from both source as well as drain end of the channel. As a result, the surface potential in the channel underneath the nanogap cavity region is affected by the neutral and charged biomolecules that binds to SiO 2 adhesion layer in the cavity. The surface potential solution is obtained by solving a 2-D Poisson’s equation assuming parabolic potential profile in the channel. The shift in threshold voltage and drain current of the device has been considered as the sensing metric for detection of biomolecules under dry environment condition. [ABSTRACT FROM AUTHOR]

Abstract: Part I of this paper dealt with the hot carrier reliability evaluation of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET involving channel recession and gate electrode workfunction engineering integration onto the conventional MOSFET, using an ATLAS device simulator. It was demonstrated that with the gate stack architecture incorporated onto the GEWE-RC MOSFET and tuning of various structural design parameters such as gate length (), negative junction depth (NJD), substrate doping (), gate metal workfunction, substrate bias (), drain bias () and gate oxide permittivity (), excellent hot carrier immunity can be achieved in terms of conduction band offset, reduced electron velocity, electron temperature, hot electron injected gate current and impact ionization substrate current. This paper focuses on the analog and large signal performance metrics in terms of linearity, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design parameters such as , NJD, , gate metal workfunction and for different substrate () and drain to source () voltages. The work, thus, proves the effectiveness of GEWE-RC for RFICs with a higher efficiency, better linearity performance; and designing and modeling of power amplifiers. [Copyright &y& Elsevier]

Abstract: The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: , , IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device’s bias point for RFICs with higher efficiency and better linearity performance. [Copyright &y& Elsevier]

Numerical assessment of Dual-Gate AlGaN/GaN MISHEMT have been presented in this paper. Analytical model has been developed and the various parameters extracted are surface potential, electric field and threshold voltage for different device specifications. Threshold voltage of nearly 0.15 V has been computed which is nearly same to that of simulated Dual-Gate MISHEMT. Simulations have been performed using ATLAS TCAD tool. Dual-Gate MISHEMT with different gate dielectric materials such as Si 3 N 4 and gate stack combinations like HfO 2 /Al 2 O 3 has been analyzed. From the results it has been inferred that at higher temperature, drain current and transconductance reduces due to lower electron sheet concentration. Different combinations of gate biases (applied at the second gate i.e. Gate 2 presented near the drain side) has been used for optimizing the device parameter for better switching performance. For DG-MISHEMT with barrier thickness of 22 nm (both the gates connected together), I ON /I OFF ratio reduces from 109 to 106 for high temperature (upto 423 K) due to reduced sheet carrier concentration. For inductance load, output drain voltage exhibits voltage range of 9.2V/2.3V for gate pulse of -8V/+2V with 30% duty cycle. Also, it is seen that as barrier thickness is varied from 18 nm to 30 nm, I OFF increases and results in reduced output drain voltages. Performance of Single Gate and Double Gate MISHEMTs has also been compared for DC-to DC converter using inductance load circuit. • Analytical model for Dual-Gate AlGaN/GaN MISHEMT. • Temperature based investigation upto 500K for Dual-Gate AlGaN/GaN MISHEMT. • Effect of barrier thickness on the I ON /I OFF ratio has been investigated. • DC-to-DC converter using Dual-Gate AlGaN/GaN MISHEMT and inductor load. [ABSTRACT FROM AUTHOR]

In this paper, effect of gamma radiation on SOI-based Tunnel Field Effect Transistor and its application as radiation dosimeter has been investigated. Throughout the paper, the exhaustive simulations have been carried out in order to investigate the generation of the electrons and holes in the oxide region and to anticipate the characteristics of the device from subthreshold region to strong accumulation/inversion region. It is found that under the radiation environment, the radiation induced degradation in threshold voltage shift and interface trap charge could not be ignored. It is concluded that the impact of radiation is visible in the subthreshold region of the drain current than on-state of drain current. Moreover, the radiation characteristics of SOI TFET have been compared with SOI MOSFET to assess its application as a dosimeter. In order to obtain the radiation characteristics of the SOI TFET, Gamma radiation model of sentaurus TCAD has been used. • Impact of gamma radiation on SOI TFET is investigated using gamma radiation model of sentaurus TCAD. • Impact of radiation is more visible in the subthreshold region than in on-state of drain characteristics. • The magnitude of threshold voltage shift in SOI TFET is order of mV. • The electrical characteristics of SOI TFET have been compared with SOI MOSFET. [ABSTRACT FROM AUTHOR]

In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (I ds -V gs ), I ON /I OFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans -conductance Generation Efficiency (g m /I ds ), have been investigated. [ABSTRACT FROM AUTHOR]