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We have fabricated bottom contact pentacene TFTs on flexible polyimide substrate and silicon substrate using different passivation layers in order to reduce the electrical instability of pentacene devices, induced by water diffusion in the film, as evidenced by electrical measurements under different environments. Experimental data show that parylene passivation layer does not introduce appreciable degradation of device characteristics and allows standard lithographic process, but it is not an effective barrier for water diffusion. The encapsulation of pentacene TFTs with an additional acryl layer does not reduce the device sensitivity to the water, whereas devices encapsulated by a parylene/acryl/aluminum triple layer do not show increase of transfer characteristics hysteresis when measured in air.

The electrical instabilities in p-channel polysilicon TFTs induced by negative bias temperature stress (NBTS) and self-heating have been investigated. From NBTS experiments performed at different temperatures and gate bias, we derived an empirical relationship that provides the T and electric field dependence of the interface state generation. To explain the device instability related to self-heating we considered a spatially non uniform interface state distribution, as a non uniform transverse electric field is present during bias stress. The interface state distribution can be deduced using the empirical relationship, determined from NBTS experiments, and considering the spatial distribution of the oxide electric field, obtained from numerical simulations. Using the so determined interface state distribution it was possible to perfectly reproduce not only the transfer characteristics but also the asymmetry observed in the output characteristics, when source/drain contacts are reverted after bias stress.

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.

Silicon dioxide films (SiO 2 ), deposited at room temperature by electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O 2 , SiH 4 and He, present excellent structural and electrical properties. However, when fabricating field effect devices it is also crucial to minimize the defect density at the semiconductor/insulator interface. We show that the interface state density, investigated in Al/SiO 2 /Si MOS capacitors, can be substantially reduced performing post-deposition annealing. In particular we studied the effects of annealing temperature and time in different gas ambient: vacuum, nitrogen and forming gas (5% H 2 + N 2 ). We found that interface state passivation mainly occurs when thermal annealing is performed after Al-contact deposition and that it is quite insensitive to the annealing atmosphere. The present results clearly suggest that the hydrogen passivation mechanism is driven by the H-containing species present in the film and a possible mechanism to explain the results is proposed.