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Lateral solid phase epitaxy (L-SPE) in non-doped or in-situ B-doped amorphous- (a-) SiGe deposited on SiO 2 patterned Si(100) wafers by in-situ postannealing in reduced pressure chemical vapor deposition system was investigated for possible heterojunction bipolar transistor (HBT) base link resistivity improvement. Using Si 2 H 6 as Si precursor gas, an epitaxial and amorphous layer was grown on the mask window and on the SiO 2 area, respectively. By inserting a-Si buffer underneath, the deposited a-SiGe surface became smoother. After the L-SPE process, an improved L-SPE length was observed due to suppressed random nucleation on SiO 2 . The L-SPE length increased with increasing postannealing time and saturated due to random poly-grain formation on the SiO 2 . At the same L-SPE time, increased L-SPE length was observed at higher temperature and at higher Ge concentration. With increasing B concentration in the a-SiGe, the L-SPE length firstly increased. However, after reaching 2 × 10 19 atom/cm 3 , the L-SPE length reduced again down to the undoped case. These results of L-SPE process might have potential to improve dynamic performance of SiGe HBT by reducing the base link resistivity by widening the monocrystalline region around bipolar window.

The solid phase epitaxy (SPE) of undoped amorphous Si (a-Si) deposited on SiO2 patterned Si(001) wafers by reduced pressure chemical vapor deposition (RPCVD) using a H2–Si2H6 gas system was investigated. The SPE was performed by applying in-situ postannealing directly after deposition process. By transmission electron microscopy (TEM) and scanning electron microscopy, we studied the lateral SPE (L-SPE) length on sidewall and mask for various postannealing times, temperatures and a-Si thicknesses. We observed an increase in L-SPE growth for longer postannealing times, temperatures and larger Si thicknesses on mask. TEM defect studies revealed that by SPE crystallized epi-Si exhibits a higher defect density on the mask than at the inside of the mask window. By introducing SiO2-cap on the sample with 180 nm Si thickness following postannealing at 570 °C for 5 h, the crystallization of up to 450 nm epi-Si from a-Si is achieved. We demonstrated the possibility to use this technique for SiGe:C heterojunction bipolar transistor (HBT) base layer stack to crystallize Si-buffer layer to widen the monocrystalline region around the bipolar window and to improve base link resistivity of the HBT.