1. FPGA high-level synthesis compile optimization algorithm based on matrix partitioning.
- Author
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ZHANG Mo-li, YANG Hai-gang, CUI Xiu-hai, and LI Yuan-qiang
- Subjects
FIELD programmable gate arrays ,HIGH-level programming languages ,COMPILERS (Computer programs) ,MATHEMATICAL optimization ,COMPUTER algorithms ,MATRICES (Mathematics) ,PARALLEL algorithms - Abstract
In order to achieve the optimal throughput by extracting parallelism in matrix during high-level synthesis, this paper proposed a matrix partitioning compile optimization algorithm to handle matrix applications, especially in multiplications. This algorithm divided data-intensive arrays into disjoint memory banks within LLVM compile framework, then merged relative iteration space, and at last, modified the data access between the iteration space and the data space. Compared with the AutoESL unfolding algorithm, experimental results show that this approach achieves 46% improvement in circuit delay and 39% reduction in resource averagely with the optimized block number. In conclusion, this high-level synthesis compile optimization algorithm based on matrix partitioning can reduce circuit delay and save resource. [ABSTRACT FROM AUTHOR]
- Published
- 2013
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