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The main theme of this Ph.D. thesis is about the use of single-walled carbonnanotubes (SWCNTs) as mechanical components for (nano) -electromechanical system(NEMS) applications. The objective of this work is to develop an industry-relevanttechnique to fabricate devices comprising of horizontally aligned individual SWCNTssuspended over the substrate (to ensure their mechanical functionality) at multiple andspecific on-chip sites in parallel, preferably in a CMOS-compatible process. The majormotivation for the choice of SWCNTs as mechanical resonators stems from their verysmall physical dimensions. SWCNTs have an extremely small diameter (usually about0.5-4 nm) and have a low spring constant, making them very flexible. Also, they havea very low linear mass density. Moreover, the enhanced mechanical robustness ofSWCNTs compared to Si and their superior transduction properties compared to Sibased materials make them a promising candidate for NEMS applications. Hence,SWCNTs are of great interest in the technology roadmap for scaling down thedimensions of mechanical devices, as they are bottom-up chemical structures and canbe relatively easily synthesized.In this thesis, we first show the successful design and fabrication of templatestructures on which parallel growth of CNTs by chemical vapor deposition (CVD) orCNT assembly by dielectrophoresis (DEP) at multiple on-chip positions could becarried out in parallel. The capacitive coupling design in the samples was takenadvantage of to assemble CNTs by DEP on to multiple electrode pairs in parallel.Electrochemical deposition (ECD) was successfully used to deposit the catalystnanoparticles required for CNT growth. It offered excellent control in depositingcatalyst nanoparticles of the required diameter and density. CNTs were grown in alocalized manner with a good control on the growth density. However, CNTs could notbe grown with the desired directionality on the templates. Therefore, the experimentsof directional CVD growth were discontinued and the process of dielectrophoresis wasused to fabricate horizontally suspended CNTs bridged between the electrode pairs.Preliminary DEP experiments with MWCNTs resulted in successful alignment ofCNTs and assembly at specific on-chip positions with high spatial selectivity. A strongdependence on the electrode angle towards the density of the deposited CNTs isobserved. Best results are obtained on the electrodes with 45O tip angle, which hadabout 40% of them bridged with single CNTs.Further, the DEP experiments were optimized with SWCNT dispersions. Theaggregation factor of SWCNTs in liquid media has been successfully quantified usingoptical absorption spectroscopy. A modified approach to estimate the SWCNTaggregation factor in dispersions was proposed and verified. The dielectrophoresisprocess was further optimized with SWCNTs, especially the effect of the frequency ofthe electric field and the concentration of the SWCNT dispersion. With the optimalDEP conditions, 40% of the electrode pairs that were bridged by nanotubes had anindividual SWCNT assembly across a total on-chip area of 1x0.1 cm2. The study ofDEP results over such large area scales is critical for predicting the yield of wafer-scaleprocesses.DC electrical measurements could be performed with the as-assembled nanotubesafter DEP. The gate dependence measurements of the drain current of the suspendedSWCNTs revealed the presence of both metallic and semiconducting nanotubesdeposited by DEP. Thermal annealing of SWCNTs in the presence of forming gas wasfound to decrease the total resistance of the nanotube device. Post -DEP Pt ECD on theelectrodes of the nanotube devices creates a Schottky barrier diode with truly rectifyingproperties.Electromechanical measurements demonstrate a significant change in thenormalized resistance of the suspended SWCNTs as a function of the actuationfrequency applied at the substrate. We observe either an increasing (upward) or adecreasing (downward) peak for different devices. The frequency at which theresistance maximum (or the minimum) is measured was found to be in reasonableagreement with the calculated mechanical resonance frequency of the suspendedSWCNT device assuming a spring model with low tension. The measured resonancefrequency of the devices ranged between 26 MHz and 35 MHz. The piezoresistanceeffect of SWCNTs could cause this significant change in the normalized resistance attheir mechanical resonance frequency. We have also established that the chirality ofthe SWCNT determines whether the SWCNT resistance increases, decreases orremains unchanged during mechanical resonance.Given the scalability of the DEP process, arrays of such devices assembled inparallel could be of interest, for instance as gas or chemical sensors. The resultsobtained in this thesis represent a successful groundwork laid towards amanufacturable technique to fabricate arrays of SWCNT resonators over a largesample area. In addition to the development and optimization of the fabricationtechnique, the electromechanical measurements of the resonators clearly establish themechanical functionality of the resonators fabricated using CMOS-compatiblematerials and methods and hence their relevance in NEMS applications. Furthermore, aclear insight into the fundamental understanding about the behavior of SWCNToscillators during mechanical resonance was obtained from our measurement data. nrpages: 151 status: published

Silicon CMOS has emerged over the last 25 years as the predominant technology of the microelectronics industry. The concept of device scaling has been consistently applied over many technology generations, resulting in consistent improvement in both device density and performance. In the last decade, the shrinking of the transistor dimensions led to short channel effects (SCEs) which decreases the device performance. As a consequence, additional improvements were needed to maintain the performance improvements such as the introduction of SiGe S/D stressors to increase the carrier mobility due to the strain in the channel, the implementation of high-K and metal gate to reduce the gate leakage and, finally, the introduction of a new 3D architecture, finFET, to further suppress the SCEs. On the other hand, no solutions exist for the scaling of the dissipated power of the transistor. In fact, the scaling of the supply voltage (Vdd) is limited by the kT/q limit of the subthreshold slope which represents a physical limit for conventional MOSFETs. As a consequence, a new operation principle is needed.In this context, the Tunnel FET (TFET) has been proposed as a potential candidate to replace the MOSFET because its carrier injection mechanism based on quantum mechanical tunneling of the electrons from valence band to the conduction band and it is not subjected to the kT/q limit. The basic embodiment of TFET is a gated p-i-n diode. This thesis addresses the design, fabrication and characterization of TFETs following a CMOS compatible processing flow. The main goal is to understand the features of band to band tunneling from an experimental point of view and identify the best processing conditions and the best architecture for TFETs. The analysis starts from silicon homojunction gated p-i-n diodes to heterojunction devices where the source is replaced with SiGe with different germanium concentrations. Two different architectures are studied: finFETs and vertical nanowires. The finFETs are used as a test vehicle to study Si TFETs since the finFET processing is already mature. On the other hand, the vertical architecture is used to implement hetero junction TFET. Finally, in view of the limitations for the basic TFET embodiments, a new architecture to boost the on current of TFETs is proposed and analyzed by TCAD simulations. CHAPTER 1: Introduction 1.1 MOSFET SCALING ISSUES 1.2 POWER CRISIS 1.3 THE QUEST FOR AN ENERGY-EFFICIENT SWITCH 1.4 THE TFET: FROM CONCEPT TO DEVICE 1.5 RESEARCH OBJECTIVE AND DISSERTATION OUTLINE CHAPTER 2: Physical Theories 2.1 INTRODUCTION 2.2 BAND-TO-BAND TUNNELING 2.2.1 The Kane’s Model and its Limitations 2.2.2 Tunneling Probability and Imaginary Wave Vector 2.2.3 Concept of Effective Bandgap 2.3 LEAKAGE MECHANISMS IN TFET 2.3.1 Theory of an Ideal Diode 2.3.2 SRH Component 2.3.3 Trap-Assisted Tunneling (TAT) 2.3.4 Arrhenius Plot 2.4 TCAD SIMULATION OF TFETS 2.4.1 Introduction 2.4.2 BTBT in Sentaurus Synopsys 2.4.3 Calibration of BTBT Models 2.5 LINE AND POINT TUNNELING 2.6 SUMMARY CHAPTER 3: Fabrication of TFETs 3.1 INTRODUCTION 3.2 FINFET INTEGRATION OF TFET 3.2.1 Design of TFETs for Planar Integration 3.2.2 Fabrication of TFET for Planar Integration 3.3 INTEGRATION OF VERTICAL NANOWIRE-BASED TFET 3.3.1 Design of vertical TFET 3.3.2 Fabrication of homojunction TFET 3.3.3 Fabrication of heterojunction TFET 3.4 SUMMARY CHAPTER 4: Basic Characterization of TFETs 4.1 INTRODUCTION 4.2 METHODS OF CHARACTERIZATION OF TFET 4.2.1 Electrical Characterization Tools 4.2.2 Methodologies and Parameters Extraction 4.3 TUNNEL FIELD EFFECT TRANSISTOR (TFET) 4.3.1 Transfer Characteristics 4.3.2 Output Characteristics 4.3.3 The subthreshold swing in TFET 4.3.4 How to Identify Band to Band Tunneling 4.4 SUMMARY CHAPTER 5: FinFET-based Si TFETs 5.1 TFET AT IMEC 5.2 IMPACT OF FIN WIDTH IN TFETS 5.2.1 Gate Geometry and Electrostatic Integrity 5.2.2 Impact of Gate Geometry on TFET 5.3 OXIDE SCALING AND TFET PERFORMANCE 5.4 TUNNELING JUNCTION ENGINEERING THROUGH DOPING 5.5 IMPACT OF THE ANNEALING CONDITIONS 5.5.1 The Trend in MOSFET 5.5.2 The Trend in TFET 5.6 SILICIDE ENGINEERING BY DOPANT SEGREGATION 5.6.1 SB TFET 5.6.2 Dopant-Segregated (DS) Schottky TFET 5.7 PERFORMANCE OF TFET 5.8 SUMMARY CHAPTER 6: Vertical Nanowire-based TFETs for Heterojunction Integration 6.1 INTRODUCTION 6.2 VERTICAL-BASED SI TFET 6.2.1 Impact of the Nanowire Diameter 6.2.2 Impact of the Gate-Source & Gate-Drain overlaps 6.3 HETEROJUNCTION VERTICAL NTFET 6.3.1 Introduction 6.3.2 Impact of the Ge Concentration and δ-layer 6.3.3 Impact of the Si Capping Layer 6.4 ANALYSIS OF THE TFET PERFORMANCE 6.4.1 Extraction of Interface Traps 6.4.2 Temperature Dependence 6.5 SUMMARY CHAPTER 7: Hybrid TFETs - a New Architecture 7.1 INTRODUCTION 7.2 THE LIMITATIONS OF THE LATERAL TFET 7.3 THE HYBRID TFET 7.3.1 Impact of Geometrical Parameters 7.3.2 Optimization of the Hybrid TFET 7.3.3 The Fabrication of the Hybrid TFET 7.4 SUMMARY CHAPTER 8: Conclusions, Future Work and Outlook 8.1 GENERAL CONCLUSIONS 8.2 FUTURE WORK AND OUTLOOK APPENDIX: Physical Characterization Methods LIST OF PUBLICATIONS nrpages: 234 status: published

After decades of scientific and technological development to fabricate ever smaller, faster and more energy efficient MOSFETs, reducing MOSFET power consumption is becoming increasingly difficult. As a possible successor to the MOSFET, the tunnel field-effect transistor (TFET) has been proposed. The topic of this thesis is to study the working principle of the TFET and to go beyond the semiclassical models towards a fully quantum mechanical modeling of the TFET which has band-to-band tunneling (BTBT) as its working principle.Semiclassical analytical models are developed to describe the two different tunneling components in a TFET: point tunneling and line tunneling.The Kane model for BTBT in direct semiconductors is extended to non-uniform fields and the envelope function formalism is extended towards heterostructures. Graphene based semiconductors are shown to have similar BTBT behavior to III-V based semiconductors. Theoretically calculating the BTBT parameters for germanium and silicon shows that direct tunneling dominates in germanium. For all direct and indirect semiconductor TFETs, it is shown there is an optimal doping concentration and material's band gap.We develop a general formalism for BTBT in indirect semiconductors capable of calculating BTBT current under a one-, two- and threedimensional potential profile. We provide a convenient expression to calculate the BTBT current based on spectral functions and prove that in the uniform field limit, the formalism reduces to the existing BTBT models. Calculating the BTBT current in the line tunneling configuration shows the impact of field-induced quantum confinement: a large shift in onset voltage and a deteriorated subthreshold slope compared to semiclassical models. The model for field-induced quantum confinement is extended to account for penetration into the gate oxide. A modified semiclassical model for BTBT is proposed and shown to be capable of taking quantum confinement into account. Two-dimensional modeling of BTBT in indirect semiconductors is carried out and it is shown that also in a two-dimensional configuration, the quantum mechanical effects are important. In particular, the subthreshold slope and on-current are degraded with respect to the semiclassical simulation. We use two-dimensional quantum mechanical simulations to show that the use of counter-doped pockets can alleviate the effects of quantum confinement. Preface Abstract Korte Inhoud Glossary Contents I. Introduction 1. Introduction II. Studying the TFET using analytical models 2. Analytical model for line tunneling 3. Analytical model for point tunneling III. Quantum mechanical modeling of BTBT in direct semiconductors 4. BTBT in direct semiconductors in non-uniform fields 5. BTBT in heterostructures 6. BTBT in graphene based semiconductors 7. BTBT in Germanium 8. Optimal doping and bandgap for TFETs IV. Quantum mechanical modeling of BTBT in indirect semiconductors 9. BTBT in indirect semiconductors 10. Field-induced quantum confinement in TFETs 11. Modified semiclassical model: quantum confinement 12. Two-dimensional modeling of BTBT 13. Study of counter-doped pockets V. Conclusions 14. Conclusions and Suggestions for Future Research Publication List Curriculum Vitae nrpages: 301 status: published

This thesis seeks to accomplish two goals. The first one is to investigate the sensitivity of MEMS to ESD stress events thereby answering the question how big a threat ESD is to the reliability of MEMS. ESD is one of the newer and less understood problems in MEMS technology, with little published literature at the start of this thesis work, as compared to better-studied issues like creep, fatigue, charging, stiction etc. This has motivated the largely experimental and exploratory work performed in the framework of this PhD. The work involved setting up test procedures and failure criteria for ESD testing in MEMS, measuring the sensitivity levels and understanding unique failure mechanisms in MEMS during ESD stress. The investigations are performed on two main electrostatically actuated MEMS test vehicles the torsional micromirror and the capacitive RF MEMS switch, and a few other related test structures.The second objective is to propose solutions for better ESD reliability of MEMS. This has been achieved either by improving the intrinsic ESD robustness through better ESD-aware MEMS design or by implementing on-chip ESD protection strategies. Both CMOS and MEMS-based ESD protection solutions are explored in the context of both CMOS-integrated and stand-alone MEMS applications.A MEMS device can typically be subjected to ESD during many stages of its production like processing, assembly, packaging, shipping and handling, and even during normal operation. Unlike semiconductor ICs, MEMS have movable components separated by air-gaps. As a consequence, two effects can occur during an ESD event. The high voltage build-up across the air-gap during ESD might make the component move causing the air gap to reduce and eventually close. When the gap closes during the ESD event, breakdown and resulting thermal damage between the electrodes can occur, causing catastrophic failure of the MEMS. When the electrical contact remains open during the ESD event, air gap breakdown or field emission can occur causing charging of the device or even permanent damage. Which of these effects occur, depends a lot on the robustness/stiffness of the MEMS. The reliability threat of ESD is complicated by the fact that it is a randomly occurring event.Therefore to study the reliability threat under ESD stress in MEMS, standard test models which simulate real-life ESD events such as the Human Body Model (HBM) were performed at the wafer level on poly-SiGe micromirrors and Al-alloy capacitive RF MEMS switches to measure their ESD sensitivity. The voltage during the ESD event was used to monitor failure, because of the high impedance of the capacitive MEMS devices. Based on these electrical measurements which detect a change in the device resistance during failure, the micromirrors and the switches were classified as extremely ESD-sensitive Class 0 devices with a failure level < 250V. All these test devices suffered catastrophic damage upon failure.However, since MEMS are designed for different non-electrical functionalities, such as optical, mechanical, motion-based, chemical, thermal etc, the correct point of failure can be determined only by comparing their functionality measurements before and after ESD stress. It was noticed through measurements that RF MEMS switches often suffered functional failure at ESD stress levels lower than the catastrophic failure level detected electrically. It is therefore mandatory that functionality tests on MEMS be performed during and after ESD to conclusively detect failure. Customized test setups were built for this purpose by integrating a portable probe-mountable HBM ESD tester with a Laser Doppler vibrometer for out-of-plane motion measurements. Simultaneous measurements of out-of-plane displacement, current and voltage in the MEMS DUT were performed in-situ during ESD stress using this setup which enabled improved failure detection and deeper understanding of the failure mechanisms in MEMS during ESD. The test setup was also used together with a pressure controlled vacuum chamber to study the effect of pressure on the ESD sensitivity, which is of importance when testing for example resonators which have to function in vacuum. The ESD reliability of capacitive MEMS switches was found to be worse in vacuum than at atmospheric pressure. Having explored the ESD sensitivity and failure mechanisms in MEMS in the first part of the PhD as described above, the focus of the second part was on improving ESD robustness and implementing ESD protection for these devices. It is shown that the intrinsic ESD robustness of MEMS can be improved by varying design parameters to increase their mechanical stiffness since a direct correlation was found between the mechanical robustness of the MEMS, the pull-in voltage and the ESD failure level. The new structures showed a 200% increase in ESD robustness for micromirrors and a much larger improvement for the RF MEMS switches with intrinsic HBM robustness of up to 650V. However, this comes at the expense of an increased pull-in voltage which is undesired in most applications. Commonly implemented customer requirements in industry require at least 2kV HBM robustness for the shipped product in the case of consumer applications. For MEMS integrated in a CMOS chip or package to survive this high level of ESD stress, design improvements alone as described above are insufficient. ESD protection is therefore essential if the MEMS are to enter the market in a commercial application. Designing ESD protection or adapting from conventional CMOS ESD protection structures is challenging, because MEMS operate at high voltages and in both voltage polarities, have unique packaging and processing requirements and impose severe area and cost constraints on the ESD protection designer.To demonstrate the concept, ESD protection was implemented on a MEMS-on-CMOS process by adapting the silicon controlled rectifier (SCR), commonly used for ESD protection in CMOS devices, to a high trigger voltage and connected in parallel with a MEMS switch. The fabricated device improved the MEMS ESD robustness from 140V (Class 0) to 5kV. Other advanced bi-directional ESD protection devices with high turn-on voltages may be used in a similar manner in the future taking advantage of slower turn-on time requirements for MEMS and lower area constraints. In a pioneering concept, small torsional devices with fast response time to ESD stress and pre-defined trigger voltages were designed and developed as on-chip MEMS-based one-time ESD protection fuses. The purpose of these devices is to provide a MEMS process-compatible basic level ESD protection for stand-alone MEMS devices during handling between manufacturing and assembly into an electronic circuit. However, MEMS-based ESD protection to be used in standalone MEMS applications made entirely on a MEMS processing platform needs further development in order to compete with the ESD protection levels offered by CMOS devices.In conclusion, the ESD reliability threat in MEMS devices is real but can surely be overcome by a combination of smart design and processing, good choice of materials and a better understanding of failure mechanisms. The magnitude of the ESD challenge is more significant and exciting in the context of newer and smaller MEMS applications with increasing functionalities in the future. nrpages: 274 status: published

Het continu schalen van CMOS technologieën maakt het steeds meer uitdagend om geschikte bescherming te voorzien tegen Elektrostatische Ontladingen (ESD). Door het dunner worden van de gate-oxides worden deze meer kwetsbaar voor ESD gebeurtenissen, zelfs zodanig dat traditionele oplossingsmethoden niet meer bruikbaar worden. Momenteel zijn zowel planaire als finfet structuren geschikte mogelijkheden voor de 45 nm CMOS technologie-node en hier voorbij. De ESD-sterkte van standaard en nieuw ontwikkelde beschermingsstructuren moet daarom onderzocht worden. TCAD simulaties zullen uitvoerig gebruikt worden om dieper inzicht te krijgen in de fysische werking van deze structuren. ESD compacte modellen zullen opgesteld worden en vervolgens gebruikt in circuitontwerp met ESD bescherming. status: published

Een combinatie van elektrische karakteriseringsmethoden om de passivatie van MOS-grensvlakken te evalueren werd onderzocht en aangepast voor Ge en III-V MOS transistoren. Dit laat toe om accurate feedback te geven om de kwaliteit van de grensvlakpassivatie te verbeteren, wat een sleuteluitdaging is bij de ontwikkeling van Ge en III-V MOSFET technologie. Ge en III-V MOSFET s worden momenteel onderzocht omwille van hun hogere mobiliteit van de vrije ladingdragers dan voor Silicium, wat zou toelaten om de verdere schaling mogelijk te maken van CMOS circuits met behoud van een performantievoordeel. In dit werk werd de kwaliteit van de grensvlakpassivatie en de impact ervan op de eigenschappen van Si-gepassiveerde Ge MOSFET s onderzocht. In het eerste deel wordt het admittantiegedrag van Ge en III-V MOS-capaciteiten uitgelegd, dat sterk verschilt van dat van Si. De MOS admittantie wordt beïnvloed op verschillende manieren wanneer het substraat en de grensvlakpassivatie gewijzigd worden. Er wordt aangetoond dat verschillende fenomenen die het admittantiegedrag beïnvloeden aanleiding kunnen geven tot ernstige onder- of overschattingen van de oppervlaktetoestandsdichtheid wanneer de conductantiemethode gebruikt wordt. Er wordt ook aangetoond dat deze problemen opgelost kunnen worden door de conductantiemethode aan te passen tot een full conductance methode. Daarnaast worden ook nieuwe methoden beschreven die toelaten zwakke Fermi-niveau pinning te onderscheiden van andere bronnen van C-V frequentiedispersie. Daarnaast wordt een gepulste Q-V/C-V techniek voorgesteld die de problemen oplost van de RF C-V methode en de gepulste C-V methode voor het opmeten van sub-nm EOT gate stacks. Ge MOS DLTS metingen werden geëvalueerd. Charge pumping karakteristieken van germanium MOSFET s werden voor de eerste keer onderzocht en de geldigheid van de emissieniveautheorie werd bevestigd voor Ge MOSFET s. Om de fractie van de gemeten vangcentra in de verboden energiezone van Ge te verhogen worden lage temperatuursmetingen voorgesteld en metingen met korte transitietijden. De Ge/Si/SiO2/HfO2 gate stack vertoont niet de voortreffelijke passivatie-eigenschappen van de Si/SiO2 gate stack. Voor het Si-gepassiveerde germanium grensvlak wordt er voorgesteld dat de toestanden in de valentiebandhelft een dubbele acceptor aard bezitten, en veroorzaakt worden door de aanwezigheid van Ge segregatie bij het Si/SiO2 grensvlak. Toestanden in de conductiebandhelft zijn daarentegen van een acceptor type. De reductie van de Ge segregatie leidt tot beter gepassiveerde grensvlakken voor dunnere Si lagen en wanneer een lage temperatuur precursor gebruikt wordt voor Si groei. Het gedrag van de drempelspanning wordt uitgelegd door de aanwezigheid van de oppervlaktetoestanden. Er wordt aangetoond dat controle van de drempelspanning geen significant probleem is voor Si-gepassiveerde Ge pMOSFET s. De invloed van de aanwezige oppervlaktetoestanden op de variabiliteit van de drempelspanning en op de helling in het zwakke inversie gebied werd onderzocht. Drie fenomenen veroorzaken een degradatie van de geëxtraheerde mobiliteit: een onderschatting door stretch-out effecten ten gevolge van oppervlaktetoestanden, remote phonon verstrooiing, en Coulomb verstrooiing door oppervlaktetoestanden. De pMOS mobiliteit vertoont bovendien potentieel voor verbetering. De aanwezigheid van een hoge dichtheid van oppervlaktetoestanden legt ook de grote trends uit in de sterk gedegradeerde nMOS performantie. status: published

Contents Chapter I: Introduction 23 I.1. CMOS Device Scaling 23 I.2. Objectives of the thesis 29 I.3. Structure of the thesis 30 Chapter II: State-of-the-Art Experimental Techniques 30 Chapter III: Reliability of Devices with Fully Silicided Gate Stacks 30 Chapter IV: Reliability of Strained-Si Devices 30 Chapter V: Reliability of Devices with Multiple-Gate Architectures 31 Chapter VI: Conclusions and Future Work 31 Bibliography 32 Chapter II: State-of-the-Art Experimental Techniques 37 II.1 Introduction 37 II. 2. Bias Temperature Instability 37 II.2.1. NBTI models 38 II.2.1.1. Reaction–Diffusion (R–D) model 38 II.2.1.2. Disorder-Controlled Kinetics model 39 II.2.2. Activation energy and time dependence 41 II.2.3. Interface traps and oxide charges 43 II.2.4. NBTI recovery 46 II.2.5. Nitrogen and fluorine 47 II.2.6. Wafer orientation 48 II.2.7. BTI measurement set-up 48 II. 3. Complementary Electrical Characterization Techniques 50 II.3.1. The conventional Charge Pumping (CP) 50 II.3.2. Conventional frequency sweep 52 II.3.3. Variable Tcharge-Tdischarge-Charge Pumping: VT2CP 52 II.3.4. Stress-Induced Leakage Current (SILC) 55 II.3.5. Low-frequency Noise 58 II.3.5.1 McWhorter's (DN) Surface Modulation Noise Mechanism 60 II.3.5.2. Hooge's (Dm) Mobility Fluctuation Mechanism 61 II.3.6. Time Dependent Dielectric Breakdown (TDDB) 62 II.3.6.1. Constant current stress (CCS) 63 II.3.6.2. Constant voltage stress (CVS) 63 II.3.6.3. TDDB analysis: the Weibull distribution 64 II. 4. Conclusions 67 Bibliography 68 Chapter III: Reliability of Devices with Fully Silicided Gate Stacks 77 III.1. Introduction 77 III.2. FUSI Process Flow 79 III.2.1. Ni silicide phase formation and effective work function 79 III.2.2. Scalability of Ni FUSI gate processes and device implementation 82 III.2.3. Dual work function phase controlled Ni FUSI CMOS integration scheme 86 III.2.4. Summary 89 III. 3. Reliability Studies 90 III.3.1. Motivation 90 III.3.2.Device Processing Details and Experimental Techniques 90 III.3.3. Experimental Results 91 III.3.3.1. Effect of Gate Electrode on NBTI 91 III.3.3.2. Effect o f Back-End-of-Line Thermal Budget on BTI 96 III.3.3.3.Effects of Nitridation Conditions on BTI 99 III.3.3.4. Observations on the scalability of the BTI behaviour in sub-1nm EOT dielectrics 109 III. 4. Conclusions 111 Bibliography 113 Chapter IV: Reliability of Strained-Si Devices 119 IV. 1. Introduction 119 IV. 2. Transport Enhancement 121 IV.2.1. Electron mobility 121 IV.2.2. Hole mobility 122 IV.2.3. Piezoresistance coefficients 123 IV.2.4. Dangling bonds 126 IV. 3. Strain introduction techniques 127 IV.3.1. Stress-strain relationship 127 IV.3.2. Global strain substrates 127 IV.3.3. SiGe and Si:C Source/Drain 130 IV.3.4. Contact-Etch Stop Layers (CESL) 133 IV.3.5. Stress Memorization Technique (SMT) 136 IV. 4. Reliability Studies 137 IV.4.1. Motivation 137 IV.4.2. Device Processing Details and Experimental Techniques 138 IV.4.3. Experimental Results 140 IV.4.3.1. NBTI Characterization 140 IV.4.3.2. Charge pumping and noise measurements 145 IV.4.3.3. Impact of strain on carrier mobility in the vertical direction 148 IV.4.3.4. Electron Spin Resonance (ESR) measurements 150 IV.4.3.5. Discussion 151 IV. 5. Conclusions 153 Bibliography 154 Chapter V: Reliability of Devices with Multiple-Gate Architectures 163 V.1. Introduction 163 V.2. Types of Multiple-Gate Devices 164 V.2.1. Planar Double-Gate devices 165 V.2.2. Tri-Gate devices 165 V.2.3. Vertical Double-Gate devices 165 V.2.4. W-Gate devices 165 V.2.5. Gate-All-Around (GAA) 165 V.2.6. P-Gate devices 166 V.2.7. Summary 167 V.3. Reliability Studies 168 V.3.1. Motivation 168 V.3.2. Device Processing Details and Experimental Techniques 169 V.3.2.1. Devices used in Section V.3.3.1: (Effects of Corner Rounding on TDDB) 169 V.3.2.2. Devices used in Section V.3.3.2: (Effects of Fluorine Passivation on BTI) 169 V.3.2.3. Devices used in Section V.3.3.3: (Effects of Nitridation Techniques on BTI) 170 V.3.3. Experimental Results 171 V.3.3.1. Effects of Corner Rounding on TDDB 171 Sub-Section V.3.3.1.A. Devices without corner rounding 173 Sub-Section V.3.3.1.B. Devices with corner rounding 177 V.3.3.2. Effects of Fluorine Passivation on BTI 180 V.3.3.3. Effects of Nitridation Techniques on BTI 189 V.4. Conclusions 195 Bibliography 196 Chapter VI: Summary, Conclusions and Future Work 203 VI.1. Summary 203 VI.2. Main conclusions 203 VI.2.1. Reliability of Devices with Fully Silicided Gate Stacks 203 VI.2.2. Reliability of Strained-Si Devices 205 VI.2.3. Reliability of Devices with Multiple-Gate Architectures 206 VI.3. Future work 208 VI.3.1. Reliability of Devices with Fully Silicided Gate Stacks 208 VI.3.2. Reliability of Strained-Si Devices 208 VI.3.3. Reliability of Devices with Multiple-Gate Architectures 208 Curriculum Vitae 209 status: published