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In this brief, a harmonic-controlled substrate-integrated defected ground structure (SIDGS) resonator with tuning capacitor is proposed for the design of tunable filter. Such resonator exhibits a harmonic-controlled characteristic. The fundamental resonant frequency can be properly tuned, while the spurious resonance is controlled at much higher frequency to achieve a wide stopband. To verify the principle, a tunable bandpass filter (BPF) is designed and fabricated based on the resonator. The center frequency can be tuned from 1.75 to 2.7 GHz. Meanwhile, the stopband can extend up to 9.5 GHz with a rejection level of 20 dB for all tuning cases. The BPF also exhibits low insertion loss (i.e., 1.1–1.9 dB) and compact size (i.e., 0.07 ${\lambda _{g}}\,\,{\times }\,\,0.08\,\,{\lambda _{g}}$ , where ${\lambda _{g}}$ is the microstrip guided wavelength at the 1.75 GHz). [ABSTRACT FROM AUTHOR]

This article presents a 22.6–39.2-GHz reflectionless receiver (RX) capable of reducing the in-band intermodulation and high-order mixing products. Such RX consists of an absorptive IF amplifier, a double-balance passive mixer, and a dual-path noise-canceling low noise amplifier (LNA). The absorptive IF amplifier is utilized to suppress the out-of-band signal reflected back to mixer, which can reduce the intermodulation and high-order mixing products caused by the remixing of the out-of-band signals. Meanwhile, the dual-path noise-canceling LNA is used for achieving low noise figure (NF) in a wide frequency range. To verify the aforementioned principle, a reflectionless RX is implemented and fabricated using a conventional 28-nm CMOS technology. The measurement shows the minimum NF of 3.6 dB and the peak input third-order intercept point (IIP3) of −11.7 dBm. Besides, the proposed RX can support multi-Gb/s, 256-quadratic amplitude modulation (QAM)/1024-QAM modulation signals. [ABSTRACT FROM AUTHOR]

In this letter, a packaged bandpass filter (BPF) with a compact size of $1.5 \times 1.5 \times 0.315$ mm3 operating at 28 GHz is proposed. This BPF is implemented based on a multilayers printed circuit board (PCB) fabrication process with ultra-thin substrate. With the packaged configuration, the filter can not only reduce the circuit size and component insertion loss, but also eliminate the effect of electromagnetic (EM) radiation. To verify the mechanisms mentioned above, a packaged millimeter-wave (mm-wave) BPF with three transmission zeros is designed and fabricated. The measured results show that the proposed BPF has the merits of low insertion loss, high selectivity, and compact size. Meanwhile, this BPF can suppress harmonics with a rejection level of more than 24 dB up to 110 GHz. With these merits, the proposed BPF is attractive for 5G mm-wave application. [ABSTRACT FROM AUTHOR]

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$. The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range. [ABSTRACT FROM AUTHOR]

This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ($P_{\mathrm{ out}}$) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ($P_{\mathrm{ avg}}$) with an error vector magnitude (EVM) of −31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm $P_{\mathrm{ avg}}$ with an EVM of −35.9 dB and an average DE of 22.6%. [ABSTRACT FROM AUTHOR]

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3–7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3°, effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, $P_{\text {out}}$ of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0°, 15°, 30°, and 45° steering are measured based on monopole antennas. Meanwhile, the array achieves < 4.7% and < 5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively. [ABSTRACT FROM AUTHOR]

In this article, a 22.9–38.2-GHz dual-path noise-canceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dual-path noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively. [ABSTRACT FROM AUTHOR]

This article proposes a quad-core millimeter-wave (mm-wave) oscillator using E-M mixed-coupling resonance boosting. The mixed-coupling resonator is introduced to generate four reconfigurable resonances. The magnetic coupling and electric coupling are achieved by the symmetrically coupled transformer and coupling capacitor, respectively. A 2-D mode switch array is introduced to couple the quad-core and achieve the quad-mode switching without degrading the performance of the selected mode. Therefore, the reduction of phase noise and the extension of tuning range are achieved simultaneously. Meanwhile, the digitally controlled tail-resistor array is used to optimize the flicker noise up-conversion in wideband. Prototyped in 40-nm CMOS, the proposed oscillator exhibits a 73.2% tuning range from 18.6 to 40.1 GHz. The best phase noise at 1-MHz offset is −108.5 dBc/Hz, corresponding to an figure-of-merit (FoM) of 184.4 dBc/Hz and FoMT of 201.7 dBc/Hz. The variation range of FoM over the whole frequency range is 3 dB. The 1/ƒ3 phase noise corner is 220–620 kHz. [ABSTRACT FROM AUTHOR]

This letter proposes a low-phase-noise high-efficiency power oscillator with digitally controlled output power and frequency. The transformer-based matching network resonator is implemented to balance the quality factor and matching efficiency. The active core and the transformer are jointly optimized to achieve the required output power while achieving the low phase noise and high power efficiency. Besides, the digitally controlled cross-coupled pair array is utilized to tune the output power. To verify the mechanism mentioned above, the power oscillator is fabricated using conventional 40-nm CMOS technology with an active area of 0.19 mm2. The proposed power oscillator exhibits a 21.7% tuning range from 2.30 to 2.86 GHz. The maximum output power is 4.5 dBm with a peak system efficiency of 25.1%. Meanwhile, the measured phase noise at a 3-MHz offset is −140.36 dBc/Hz at 2.79 GHz. The corresponding figure of merit (FoM) is 189.2 dBc/Hz, and FoMT is 196 dBc/Hz. [ABSTRACT FROM AUTHOR]

A quadrature digital power amplifier (PA) with hybrid Doherty and impedance boosting (HDIB) technique is presented for deep power back-off (PBO) efficiency enhancement in the complex domain. Less power-combining ways and dc power supplies are required for proposed PA comparing to previously reported works with deep PBO efficiency enhancement. A reconfigurable matching network (RMN) based on a novel reconfigurable transformer is proposed with more freedom to achieve a flexible load impedance tuning range of the sub-PAs. The characteristics of the reconfigurable transformer based on tunable inductors are analyzed. Efficiency enhancement is achieved at 3-/6-/9-/12-/15-dB PBOs without any supply switching or PA short-switches. The PA is fabricated in 40-nm CMOS technology with a core size of 0.83 mm2. Operating at 2.3–3.4 GHz, it introduces 24.2-dBm peak Pout with 38.5% peak drain efficiency (DE) at 2.8 GHz. It achieves 38.5%/29.6%/18.4% at 2.8 GHz and 34.7%/26.6%/17.8% DE at 3.3 GHz for 0-/6-/12-dB PBO, 39.3%/29.5%/14.9% at 2.8 GHz, and 35.3%/27.9%/15.9% DE at 3.3 GHz for 3-/9-/15-dB PBO, respectively. For 10-MHz 256-QAM modulation signal, it delivers 16.22-/15.50-dBm average Pout with EVM of −32.3/−33.0 dB, average DE of 24.6%/22.7%, and ACLR of −33.20/−31.54 dBc at 2.8/3.3 GHz, respectively. For 20-MHz 64 QAM modulation signal, it exhibits 16.42-/15.52-dBm average Pout with EVM of −29.1/−29.3 dB, average DE of 24.9%/22.78%, and ACLR of −30.78/−30.74 dBc at 2.8/3.3 GHz, respectively. [ABSTRACT FROM AUTHOR]

In this letter, a compact wideband bandpass filter (BPF) with a wide stopband is proposed based on the substrate integrated defected ground structure (SIDGS) and folded stepped-impedance resonator (FSIR). Such a SIDGS resonator can not only allocate a specific resonance with compact size but also introduce the different harmonic positions compared with a traditional microstrip line resonator. Meanwhile, due to the discrepant harmonic positions of proposed SIDGS and FSIR, a wide stopband response can be achieved using a compact stacked-coupled scheme. To verify the mechanism, a miniaturized wideband BPF operating at 1.69 GHz (i.e., ƒ0) is implemented and fabricated. A measured wide stopband up to 11.8 ƒ0 with a 20-dB rejection level is achieved. [ABSTRACT FROM AUTHOR]

In this article, a wideband quasi-circulator (QC) with the low noise figure (NF) and high 1-dB compression point (P1dB) is proposed. The slotline-based 180° hybrid is introduced to achieve the wideband high transmitter-receiver (TX-RX) isolation. Meanwhile, the bidirectional in-phase stage and the nonreciprocal out-of-phase stage are utilized to obtain specific power-split ratios for the low insertion loss and high antenna-transmitter (ANT-TX) isolation. By using the unequal power split, the proposed QC is without the fundamental 3-dB loss seen in reciprocal ANT interfaces. Besides, to further enhance the TX-RX isolation within a wideband, a reconfigurable inter-stage matching network based on a varactor-tuned capacitor is implemented. To verify the mechanisms mentioned above, a reconfigurable wideband QC operating at 1.75–2.9 GHz is implemented and fabricated. The total power consumption is 224 mW. The measurement exhibits in-band TX-RX isolation of 27–58 dB. The TX-ANT and ANT-RX insertion losses are 4.3–5.0 dB and 1.0–1.9 dB, respectively. The QC also achieves the minimum in-band ANT-RX NF of 3.4 dB. Meanwhile, the measured TX-ANT and ANT-RX IIP3s are 39.4 and 32.5 dBm, respectively. The TX input P1dB is greater than 28.78 dBm, while the RX input P1dB is 23 dBm. The TX-induced ANT-RX P1dB is measured to be 28 dBm. [ABSTRACT FROM AUTHOR]

In this letter, a novel substrate integrated defected ground structure (SIDGS) resonant cell is proposed. Such SIDGS resonant cells can not only introduce an ultrawide stopband for spurious suppression but also achieve low radiation loss in a wideband, which can be easily implemented in passive circuits with high performance. To verify this mechanism, a filtering power divider (FPD) using the folded stepped-impedance scheme is developed. Here, two coupled SIDGS resonant cells are cascaded at the arms of the power divider to achieve a filtering response with ultrawideband harmonic suppression. The fabricated FPD is operated at 2.87 GHz (i.e., the passband center frequency $f_{0}$) with a 3-dB fractional bandwidth (FBW) of 23%, which exhibits the 28-dB attenuation upper stopband with a low radiation loss even up to 25 GHz (i.e., 8.71 $f_{0}$). [ABSTRACT FROM AUTHOR]

In this letter, a wideband watt-level digital power amplifier (DPA) with a balance-compensated matching network is proposed for polar transmitters. The balance response of the differential to the single-ended transformer is enhanced by a series-loaded compensation capacitor, which leads to the improvement of the DPA efficiency. To verify the mechanisms, a prototype DPA is fabricated in conventional 40-nm CMOS technology. The proposed DPA operates over 1.2–2.8 GHz and exhibits a peak output power of 32.4 dBm at 2 GHz and a peak drain efficiency of 53.8% at 1.8 GHz. It supports 50-MHz 64-quadratic-amplitude modulation (QAM) with average output power ($P_{\text {avg}}$) of 25.37 dBm, error vector magnitude (EVM) of −26.97 dB, adjacent channel power ratio (ACPR) of −29.61 dBc, and 10-MHz 1024-QAM with $P_{\text {avg}}$ of 22.14 dBm, EVM of −35.75 dB, and ACPR of −35.37 dBc, respectively. [ABSTRACT FROM AUTHOR]

In this article, two types of substrate-integrated defected ground structure (SIDGS) resonant cells with wide upper stopband and low radiation loss are presented for filter implementation. Such SIDGS resonant cells are composed of two dissimilar DGSs surrounded by the bottom ground and metal-vias, which cannot only introduce wide stopband with low radiation loss but also be flexible for integration. Based on the aforementioned SIDGS resonant cells, single- and dual-band bandpass filters (BPFs) are designed and fabricated. The single-band BPF centered at 2.40 GHz exhibits an ultrawide upper stopband up to 19.7 GHz with a rejection level of 31 dB, whereas the measured stopband total loss (i.e., including radiation, metal, and substrate loss) remains about 30% up to 19.3 GHz. The dual-band BPF operated at 2.10 and 3.78 GHz exhibits an ultrawide upper stopband up to 17.8 GHz with a rejection level of 23 dB, whereas the measured stopband total loss is less than 16% up to 11.4 GHz. [ABSTRACT FROM AUTHOR]

Satisfying the increasing volume of data streaming in modern wireless systems will demand energy-efficient RF front ends with gigabit data rates, high integration levels, and low cost. The power amplifier (PA) is the last door in the RF front end for both the digital and analog kingdoms, one that greatly affects the quality of service of the wireless link [1]. Thus, breaking through barriers (i.e., output power, linearity, efficiency, operation band, and even multifunction) in PA design is of paramount importance right now [2]. Consequently, with the aim of meeting the modern requirements of multistandard wireless applications, such as 5G, narrowband Internet of Things (NB-IoT), wireless local area network (WLAN), and future smart communications, various mixed-signal PAs have been developed and proposed in recent years. [ABSTRACT FROM AUTHOR]

A compact high-resolution reconfigurable phase-tuning line (RPTL) based on self-shielded 3-D interdigital capacitors is presented in this letter. Such a capacitor with high- $Q$ and self-shielded characteristics is used to implement the digitally switchable capacitor array in the RPTL, which is integrated with a coplanar waveguide and can lead to merits of the low loss, high phase-tuning resolution, and compact size. Meanwhile, the grounded shield is utilized in the RPTL to further reduce the loss. To verify the mechanisms of aforementioned structure, a 6-bit digital controlled RPTL is implemented and fabricated using a 40-nm CMOS technology. At 30 GHz, the measured loss of the proposed RPTL is 2.1 dB, while a tuning resolution of 0.38° with an RMS phase error of 0.25° is achieved. [ABSTRACT FROM AUTHOR]

In this letter, a wideband reflectionless filtering 90° coupler with a wide stopband is proposed, which consists of two parallel connected channels. The main channel is implemented by the stacked cross coupled-lines, which can not only introduce a filtering 90° coupler with a compact size but also achieve a wide-stopband response. Meanwhile, the stepped-impedance microstrip line, loaded cross-stub, and resistor are used to construct the absorptive bandstop filter in the auxiliary channel, which absorbs the reflected signal from the filtering coupler to obtain the wideband reflectionless operation. To verify the aforementioned mechanism, a wideband reflectionless filtering 90° coupler operating at 1.47–2.53 GHz is implemented and fabricated. The measured results demonstrate that the proposed coupler has the merits of low passband insertion loss, low amplitude and phase imbalances, wide stopband, and wide reflectionless range. [ABSTRACT FROM AUTHOR]

This article presents a broadband quadrature digital transmitter (TX) architecture for part of the fifth-generation new radio (5GNR) frequency range 2 (FR2) and backhaul communication. Synthesized impedance variation compensation (IVC) is introduced to improve the efficiency by manipulating the load impedance variation of sub-arrays in the power digital-to-analog converter (power-DAC) at mm-wave. The operation bandwidth is extended by 5 GHz with reconfigurable circuits of output matching in power-DAC, interstage matching, and quadrature signal generator. A mixed-signal sign map is adopted to provide LO gain as well as constellation quadrant selection. As a proof of concept, a $2\,\,\times10$ -bit 20–32-GHz quadrature digital TX is designed and fabricated in 28-nm CMOS technology. With a 1-V supply, the proposed quadrature digital TX achieves the peak output power of 19.02 dBm at 22.5 GHz, the peak drain efficiency of 34.4% at 22 GHz, and the peak system efficiency of 22.1% at 22 GHz. At 23/28 GHz, it demonstrates the EVM of −28.9/−28.4 dB, the average power of 9.96/9.17 dBm, and adjacent channel power ratio (ACPR) of −33.6/−33.3 dBc for 3-Gb/s 64-QAM modulation, respectively. It also supports 1-Gb/s 256-QAM modulation signal. [ABSTRACT FROM AUTHOR]

Advances in wireless communication are propelling the development of microwave applications for smart cities, the Internet of Things, and 5G wireless communications. However, in practice, blockages, such as hands, bodies, and walls, severely limit microwave signal propagation. Thus, good-quality relay systems are highly valuable because they can significantly improve network coverage and system throughput. Relay systems can also save energy by switching operation mode according to the working environment. In this article, a relay transceiver is introduced that was awarded first place in the Adaptive Relay Transceiver Student Design Competition (SDC) during the IEEE Microwave Theory and Techniques Society (MTT-S). 2019 International Microwave Symposium (IMS2019). This competition category was sponsored by MTT-S Technical Coordinating Committee 20. [ABSTRACT FROM AUTHOR]

A wideband hybrid mode-switching push–push oscillator with low phase noise is presented in this paper. To achieve the wide tuning range, the inductive and capacitive hybrid mode-switching technique is proposed for the first time. It introduces more freedom of design parameters (i.e., inductance and capacitance) in the resonant tank. Under certain tuning range requirement, the hybrid mode-switching oscillator achieves higher input impedance of the resonator compared to the conventional mode-switching oscillators. Meanwhile, a transformer-coupled inductor ring with symmetrical layout configuration is proposed to realize the switch-less hybrid mode switching, which further improves the circuit performance at sub-THz. Therefore, a good phase noise performance can be obtained within a wide tuning range, which leads to a relaxed tradeoff between the phase noise and tuning range. To verify the aforementioned mechanism operating at sub-THz band, a hybrid mode-switching oscillator based on the dual-mode push–push topology is proposed and fabricated in a conventional 28-nm CMOS technology. The measured results show a 21.7% tuning range with the center frequency of 169.6 GHz and a state-of-the-art FoMT of −180.6 dBc/Hz. The core circuit only occupies 0.039 mm2, while drawing 95 mW with a 0.9-V supply. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive synthesis using the particle swarm optimization (PSO) for implementations of resonator-coupled filters is proposed. The coupling matrix of in-band filtering response is achieved and optimized by the PSO-based synthesis. Meanwhile, the stopband coupling matrix of the filter is predicted based on the combination of extra resonant nodes representing stopband spurious and parasitic effect of input/output ports. In addition, an enhanced accurate prediction of filter performance is calculated by the proposed approach, considering the practical fabrication tolerance on filter design. To verify principles mentioned earlier, various resonator-coupled filters are implemented. The calculation, EM-simulation, and measurement of filters show good agreements in both passband and stopband. [ABSTRACT FROM AUTHOR]

The needs of multiband communication continue to grow, leading to an increase in the number of RF bands. Therefore, to meet system requirements for efficient operation in a compact size, as well as develop multifunction applications, reconfigurable and miniaturized filters using a single signal path are essential. [ABSTRACT FROM PUBLISHER]

In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]

In this letter, a compact wideband phase shifter using a microstrip self-coupled line and a broadside-coupled microstrip/CPW (BCMC) structure is proposed for multiphase feed-network. With a uniform phase reference, such a phase shifter can achieve multiphase responses by adjusting instinct self- and broadside couplings for constant phase shifts within a wideband. Then, with the combination of proposed phase shifters and a microstrip Wilkinson power divider, a multiphase feed-network can be implemented. To verify the mechanisms mentioned earlier, a wideband feed-network is fabricated with measured multiphase responses (i.e., 0°, 5.625°, 11.25°, 22.5°, 45°, 90°, and 180°) and maximum insertion loss of 1.57 dB from 1.7 to 2.3 GHz. [ABSTRACT FROM PUBLISHER]

In this letter, a miniaturized on-chip stacked-spiral-coupled (SSC) Marchand balun is proposed with wideband operation, i.e., fractional bandwidth (FBW) >125%. To improve the inband balance responses (i.e., amplitude- and phase-balances), the self-coupled compensation line and center-tapped ground-shield with deep trench are introduced. To verify the mechanism of structures mentioned above, a balun operating from 6.5-28.5 GHz is implemented and fabricated using a 0.13- \mu \mathrm m SiGe technology. The measured amplitude- and phase-imbalances of the on-chip balun are ±1 dB and ±1.65°, respectively. [ABSTRACT FROM PUBLISHER]