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This paper proposes a highly scalable sensor design for late transition detection in FPGA based platforms. Transition delays occur because of aging mechanisms such as Biased Temperature Instability (BTI) and Hot Carrier Injection (HCI). We propose a sensor clock (SCLK) that is a function of minimum slack time of a set of paths selected for age monitoring. There will be one such clock for many sensors as are needed in an entire FPGA. Our proposed sensor architecture makes it possible for a single SCLK to be shared by all sensors. Additionally, the proposed sensor occupies one slice (basic FPGA logic block), which leads to low area, power, and performance overhead. Using Artix-7-based board, experimental results demonstrate that the proposed aging sensor detects aging earlier than existing sensors and provides less power and performance overheads. [ABSTRACT FROM AUTHOR]

Abstract: Leakage power has grown significantly and is a major challenge in SoC design. Among SoC''s components, clock distribution network power accounts for a large portion of chip power. This paper proposes to deploy sleep transistor insertion (STI) in the clock tree of datapaths in ASICs or in general-purpose processors in order to reduce leakage power. It characterizes the effect of sleep transistor sharing and sizing on clock tree wakeup time, leakage power, and propagation delay. It then uses these characteristics during leakage power optimization. It describes a post synthesis sleep transistor insertion (PSSTI), a heuristic clustering algorithm for sleep transistor insertion with the objective of total power minimization in a given clock tree. Sleep transistor sharing and sizing are deployed in order to meet the clock skew and wakeup delay constraints. The potential benefits of STI in ASIC design are evaluated using a standard industrial VLSI-CAD flow including sleep-transistor insertion and routing after the clock synthesis and place-and-route of the benchmark circuits. The results show that the clock tree leakage power is reduced by 19–32% depending on the topology of the synthesized clock tree. We also apply PSSTI in the clock tree of the datapaths in general-purpose processors using architectural control of the sleep mode. This achieves a reduction in the leakage power and the dynamic power of the clock tree within different datapath components (adder, multiplier, etc.) of as much as 80%. This approach is also applicable to other on-chip structure where inverters are large in size and commonly used, e.g. SRAMs or networks-on-a-chip, which combined with the clock tree savings will significantly reduce processor or ASIC overall power consumption. [Copyright &y& Elsevier]

An introduction to the journal is presented in which the editor discusses various reports within the issue on topics related to reconfigurable computing including calculation of logarithm function of data, graphical processing units (GPUs), and used of dynamic instruction merging (DIM) approach.