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The utilization of switched inductors, involving parallel charging and series discharging of inductors, is extensively embraced in diverse DC–DC converters for attaining high voltage gain; nevertheless, the stress on switch voltage and diode current escalates considerably with an increased count of inductors integrated into the switched inductors network. In the classical multistage switched inductor converter, the switch voltage aligns with the output voltage, and the diode experiences a high current as the number of stages increases. This research recommends a DC–DC multistage converter for energy conversion and high voltage gain with low stress. In this paper, a novel multistage switched inductor converter is introduced and designed to attain higher voltage gain while mitigating the stresses on switch voltage and diode current. The proposed circuit is created by replacing the standard multistage switched inductor converter's possible diodes with power switches. All of the switching devices are connected in such a way that the output voltage and input current are shared by all of the switches and diodes, respectively. As a consequence, the voltage stress on switches and the current stress on diodes are comparatively low, resulting in a high efficiency compared to a typical multistage switched inductor converter. It's interesting to note that the proposed converter and a typical multistage switched inductor converter both require the same amount of components. Different operation modes, analysis, a non‐ideal model, and a comparison of the suggested and recently constructed converters are discussed. The effectiveness and performance of the circuit are validated experimentally. [ABSTRACT FROM AUTHOR]

There is a continuously evolving, unmet need for RF (Radio Frequency) Filters that operate contiguously over multiple frequency octaves or bands. Unlike traditional switched filter banks, these new filters require similar levels of RF performance but with more filters and a smaller overall footprint. Legacy systems typically operate over a sub-octave and filters meant to break down information from the aperture to sub-bands (octave wide) or a little less. These wideband filters, pre-LNA (low noise amplifier), were minimal loss but very large. This paper will examine two new solutions to miniature, wideband, and contiguous filtering, their different capabilities, and where the new filter technologies can enable new overall system capabilities. The commercial (cell phone) vs DoD (Department of Defense) requirement differences which drive very different needs for RF filters highlight the SWAP-C (Size, Weight, and Power - Cost) challenge as wideband, contiguous vs. not, is considered. [ABSTRACT FROM AUTHOR]

Ulcers and chronic wounds are a large and expensive problem, costing billions of pounds a year and affecting millions of people. Electrical stimulation has been known to have a positive effect on wound healing since the 1960s and this has been confirmed in numerous studies, reducing the time to heal, and the incidence of adverse events such as infections. However, because each study used different parameters for the treatment, inclusion criteria and metrics for quantifying the success, it is currently hard to combine them statistically and gain a true picture of its efficacy. As such, electrical stimulation has not been universally adopted as a recommended treatment for various types of wound. This paper summarises the biological basis for electrical simulation treatment and reviews the clinical evidence for its effectiveness. Notable is the lack of research focused on the electrodes used to deliver electrostimulation treatment. However, a significant amount of work has been conducted on electrodes for other medical applications in the field of e-textiles. This e-textile work is reviewed with a focus on its potential in electrostimulation and proposals are made for future developments to improve future studies and applications for wound healing via electrical stimulation. [ABSTRACT FROM AUTHOR]

As a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose a method for calculating the DC source amplitude in an extended multilevel inverter (MLI) structure so that the maximum number of levels and the output voltage waveform are as close as possible to the sinusoidal wave with minimum total harmonic distortion (THD). For the developed structure, three algorithms are suggested to determine the amounts of DC voltage resources. The first important point about choosing the right amounts for the DC resources is that the number of levels should be as large as possible, and the second important point is that the intervals between the levels should be the same throughout the waveform. By observing these two points, the output voltage waveform can be as near as possible to the sinusoidal wave that we want. In this study, we used iteration-based methods to find suitable values for DC sources. Simulation results are offered to confirm the capability of the extended multilevel converter. After we solved the problem through calculation and analysis, a code was written in MATLAB with the aim that this time the code will tell us for what values of DC sources we will have the largest number of levels and as we expected, the output of the MATLAB code confirmed the correctness of the calculations. [ABSTRACT FROM AUTHOR]

Integrated photonics is a cutting-edge field that merges optics and electronics on a single microchip, revolutionizing how we manipulate and transmit light. Imagine traditional bulky optical systems condensed onto a chip smaller than a fingernail, enabling faster communication, more efficient sensors, and advanced computing. At its core, integrated photonics relies on guiding light through waveguides etched onto semiconductor substrates, analogous to how wires conduct electricity in traditional electric circuits. These waveguides can route, modulate, and detect light signals with unprecedented precision and speed. This technology holds immense promise across various domains. Despite its immense potential, integrated photonics faces challenges, including manufacturing complexities and integration with existing electronic systems. However, ongoing research and advancements continue to push the boundaries, promising a future where light-based technologies seamlessly integrate into our everyday lives, powering a new era of innovation and connectivity. [ABSTRACT FROM AUTHOR]

Abstract The utilization of switched inductors, involving parallel charging and series discharging of inductors, is extensively embraced in diverse DC–DC converters for attaining high voltage gain; nevertheless, the stress on switch voltage and diode current escalates considerably with an increased count of inductors integrated into the switched inductors network. In the classical multistage switched inductor converter, the switch voltage aligns with the output voltage, and the diode experiences a high current as the number of stages increases. This research recommends a DC–DC multistage converter for energy conversion and high voltage gain with low stress. In this paper, a novel multistage switched inductor converter is introduced and designed to attain higher voltage gain while mitigating the stresses on switch voltage and diode current. The proposed circuit is created by replacing the standard multistage switched inductor converter's possible diodes with power switches. All of the switching devices are connected in such a way that the output voltage and input current are shared by all of the switches and diodes, respectively. As a consequence, the voltage stress on switches and the current stress on diodes are comparatively low, resulting in a high efficiency compared to a typical multistage switched inductor converter. It's interesting to note that the proposed converter and a typical multistage switched inductor converter both require the same amount of components. Different operation modes, analysis, a non‐ideal model, and a comparison of the suggested and recently constructed converters are discussed. The effectiveness and performance of the circuit are validated experimentally.

The performance of the power converter bus bar is not only determined by its normal operational design, but also related to its fault ride-through ability consideration. Conventional busbar design only takes the normal operational performance into account. This article proposes an optimal busbar design method for the modular multilevel converter (MMC) submodule, which takes both the normal and fault ride-through performance into account. The normal operational design is to realize low stray inductance and balanced inductance distribution between parallel capacitor branches. The basic structural design guideline for the MMC submodule is presented. Taking both the stray inductance and manufacturing cost into account, the optimal layout of the busbar is proposed. To balance the capacitor branch currents, the mathematical model of the busbar stray inductance is built. The influence of different busbar structures on the stray inductance is analyzed. The analysis is verified by simulation results. To improve the fault ride-through capability, special consideration is taken into account to reduce the thermal and mechanical stress at the weakest point. Simulation and experimental results verify the efficacy of the proposed approaches. [ABSTRACT FROM AUTHOR]

Currently, the study of energy balancing in cascaded multilevel inverter cells is desirable due to the growing interest in implementing systems that minimize losses, ensure delivery of the maximum amount of power to the load, contribute to system reliability, and at the same time minimize the use of resources for its implementation. One of the ways to carry out energy balancing without resorting to additional topology is by modifying conventional modulation techniques. In this letter, the FPGA implementation of modulation strategies for energy balancing purposes is carried out. First, three conventional techniques are addressed: 1) phase-shifted carrier disposition; 2) level shift per carrier cycle; and 3) level shift per modulator cycle. Subsequently, the implementation of an alternative modulation strategy that performs energy balancing in the cascaded multilevel inverter, minimizing the use of digital resources, is presented. [ABSTRACT FROM AUTHOR]

Abstract As a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively.