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The utilization of switched inductors, involving parallel charging and series discharging of inductors, is extensively embraced in diverse DC–DC converters for attaining high voltage gain; nevertheless, the stress on switch voltage and diode current escalates considerably with an increased count of inductors integrated into the switched inductors network. In the classical multistage switched inductor converter, the switch voltage aligns with the output voltage, and the diode experiences a high current as the number of stages increases. This research recommends a DC–DC multistage converter for energy conversion and high voltage gain with low stress. In this paper, a novel multistage switched inductor converter is introduced and designed to attain higher voltage gain while mitigating the stresses on switch voltage and diode current. The proposed circuit is created by replacing the standard multistage switched inductor converter's possible diodes with power switches. All of the switching devices are connected in such a way that the output voltage and input current are shared by all of the switches and diodes, respectively. As a consequence, the voltage stress on switches and the current stress on diodes are comparatively low, resulting in a high efficiency compared to a typical multistage switched inductor converter. It's interesting to note that the proposed converter and a typical multistage switched inductor converter both require the same amount of components. Different operation modes, analysis, a non‐ideal model, and a comparison of the suggested and recently constructed converters are discussed. The effectiveness and performance of the circuit are validated experimentally. [ABSTRACT FROM AUTHOR]

As a key component of high‐performance switches and routers, the packet forwarding engine (PFE) is mainly responsible for selecting the appropriate output port for tens of thousands of packets within an extremely short time frame. However, the performance of PFE is determined by the selected group membership algorithm. This paper puts forth a hybrid strategy–caching scalar‐pair and vectors routing and forwarding (CSVRF), consisting of virtual output port bitmap caching (VOPBC) and fractional‐N SVRF to address major multicast forwarding issues such as scalability by using content addressable memory. In CSVRF, a virtual output port bitmap cache is introduced, which includes the most popular combinations of output port bitmap and divides the big scalar‐pair into N sub‐groups to achieve parallel compute and the reusability of less bit‐length prime. The results demonstrate that the memory space and the forwarding latency are effectively reduced compared with previous work. In space efficiency, it only required 10% memory space compared with the original SVRF/fractional‐N SVRF, decreased 10% memory usage compared with pure VOPBC and nearly improved 1 to 4 orders of magnitude of packet processing time compared with the original SVRF and the fractional‐N SVRF respectively. [ABSTRACT FROM AUTHOR]

In this paper, Artificial Neural Networks (ANNs) for diagnosing multiple open‐switch faults in three‐phase PWM (Pulse Width Modulation) converters are designed. For single and double open‐switch faults in the converters, there are 21 types of fault modes, causing distorted phase currents. Since these abnormal currents can induce secondary faults in peripherals, the open‐fault diagnosis is essentially required. In this paper, a two‐step technique based on ANNs is utilized for the diagnosis of the multiple open‐switch fault. First, dc and harmonic components of the currents are extracted by using an ADALINE (Adaptive Linear Neuron). In the first step, the ANN categorizes fault modes into six sectors by using dc components in the three‐phase plane. In the second step, the ANN localizes fault modes by using dc components and the ratio of d–q axes currents THDs (Total Harmonics Distortions) in each sector. Especially, both switches open‐faults in the same legs are localised by counting the sampled zero current of the fault currents. The proposed two‐step technique allows a simple design of the ANNs for the diagnosis, and a short execution time about 22 s. Simulations and experiments for a 3.7 kW three‐phase PWM converter confirmed the validity of the proposed diagnostic method. [ABSTRACT FROM AUTHOR]

This paper presents a novel converter topology for six-phase switched reluctance motor (SRM) drives, which reduces the number of switches and diodes by half, compared with the conventional asymmetric half-bridge (AHB) converter, and needs no additional energy storage component. A dynamic model of a six-phase SRM is developed in the MATLAB/SIMULINK environment and conventional control technique is applied to the proposed converter, demonstrating successful operation with modified conventional current control technique, lower converter losses, and higher system efficiency compared with the AHB converter. Furthermore, a direct torque control (DTC) method has been proposed for the novel converter to further reduce the torque ripple. Experimental tests comparing the proposed converter with the AHB are described and verify the predictions of the simulations. [ABSTRACT FROM AUTHOR]

Field-programmable gate array (FPGA)-based simulation system is applied in real-time electromagnetic transient (EMT) simulation for small time-step simulation. However, the FPGA-based simulation system requires handcrafted hardware description language (HDL) and significant design efforts. This paper explores FPGA-based EMT real-time simulation system design using high-level synthesis (HLS) technology to accelerate the design process and improve the flexibility, because high-level language can be transferred into HDL using HLS. Furthermore, loop unroll and pipeline optimisation directives are analysed and applied for HLS to improve the computation speed of the components. The system can simulate various components, including switches, R-L-C, voltage sources, current sources, and transmission lines. Especially, the system adopting double-precision floating-point calculation can support the network with 74 nodes and achieve 2 us for each small time step on Xilinx Virtex7-690 T FPGA. Comparison of simulation results from offline simulation tools with those from the proposed simulation system validates the correctness of the FPGA-based EMT simulation system using HLS technology. [ABSTRACT FROM AUTHOR]

This study proposes a three-phase direct matrix converter (DMC) topology based on an improved quasi-Z source (QZS) network. The proposed topology shows the following features: (i) Improve the voltage transmission ratio of traditional DMC. (ii) The voltage and current on the output side can be affected by the input side to the minimum, which minimises the harmonic content of the output current. (iii) Due to the existence of the improved QZS network, the three bidirectional switches of each output phase bridge arm are turned-on at the same time, which improves the reliability of the system. (iv) The improved QZS network has an input LC filter function, and no additional filter circuit is required on the input side. This study analyses the topological structure of the improved QZS-DMC and elaborates its boost working principle. On this basis, an improved dual space vector modulation strategy with shoot-through zero vector is proposed, which can effectively reduce the loss of the switch tube and improve the output waveform quality of the converter. Simulation and experimental results verify the proposed topology and strategy. [ABSTRACT FROM AUTHOR]

In this study, a crosspoint‐queued (CQ) switch that features a buffer size larger than one and employs the work‐conserving random scheduling algorithm under uniform Bernoulli i.i.d. traffic is investigated through both theoretical analysis and simulation. The effect of the crosspoint buffer state on switch performance is modelled and quantified. A novel method for calculating the throughput and delay of a CQ switch with a given switch size, input load, and buffer size is proposed. Compared with existing models, the proposed calculation model offers a simpler and more accurate result, and can serve as a theoretical guide in designing high‐speed switch fabrics. [ABSTRACT FROM AUTHOR]

Power loss reduction can be considered as one of the main purposes for distribution system operators. Reconfiguration is an operation process used for this optimisation by means of changing the status of switches in a distribution network. Recently, all system operators tried their best in order to obtain well‐balanced distribution systems to decrease the operation cost, improve reliability and reduce power loss. This study presents an efficient method for solving the multi‐objective reconfiguration of radial distribution systems with regard to distributed generators. The conventional distribution feeder reconfiguration (DFR) problem cannot meet the reliability requirements, because it only considers loss and voltage deviation as objective functions. The proposed approach considers reliability, operation cost and loss simultaneously. By adding the reliability objective to the DFR problem, this problem becomes more complicated than before and it needs to be solved with an accurate algorithm. Therefore this study utilises an Enhanced Gravitational Search Algorithm called EGSA which profits from a special mutation strategy in order to reduce the processing time and improve the quality of solutions, particularly to avoid being trapped in local optima. The proposed approach has been applied to two distribution test systems including IEEE 33 and 70‐node test systems. [ABSTRACT FROM AUTHOR]

A new single‐phase asymmetrical multilevel inverter (MLI) is presented in this study. The proposed topology generates a staircase output voltage waveform with a maximum number of levels using less number of components compared to several existing and recent topologies. The basic module consists of a combination of two isolated DC sources with ten switches that produce all the possible number of levels. Other advantages of the proposed MLI include improved output voltage performance and a low blocking voltage of the switches. The low switching frequency pulse width modulation (LSF‐PWM) technique has been used for the generation of gate pulses. In the LSF technique, selective harmonic elimination (SHE) and fundamental switching frequency PWM techniques have been discussed for the better output voltage waveform. The optimised switching angles with SHEPWM has been calculated using particle swarm optimisation considering the different combination of the elimination of lower order harmonics. Simulation work was carried out using MATLAB/SIMULINK, and a prototype was implemented to validate the proposed MLI module. Simulation and experimental results have been provided in the study to show the performance of the proposed topology with these modulation techniques. [ABSTRACT FROM AUTHOR]

In this study, a novel multi‐source switched‐capacitor converter is proposed. In the proposed topology, the capacitor charging is carried out in a self‐balancing form eliminating the need for additional balancing circuits. After that, the design principle of the proposed inverter is discussed in details. A comparison study between the proposed topology and other existing topologies is provided next. According to this comparison, the proposed topology requires fewer components, such as DC power supplies, switches, capacitors, and diodes. Further, the simulation results for 15‐level and 127‐level and the experimental results for a 15‐level inverter are provided. The simulation and experimental results are in close agreement and verify each other. [ABSTRACT FROM AUTHOR]

The active clamp flyback (ACF) converter utilising gallium nitride (GaN) devices with high‐switching frequency and high efficiency is impressive in system miniaturisation for AC–DC adapters. Owing to poor reverse conduction of GaN devices, the improper dead time between two switches can cause large power consumption in high frequency. This study proposes a dynamic dead time optimisation technique for GaNs ideal zero‐voltage switching (ZVS) to address the issue. It adjusts the clamp switch on time to avoid large reverse conduction voltage stress on the main switch in different loads conditions. In addition, a new control scheme for clamp switch is introduced for enhancing efficiency in light to medium load. These techniques are experimentally verified on a 45 W (20 V/2.25 A) prototype of an ACF converter with a field‐programmable gate array. The controller enables the system to operate at 1 MHz and dynamically modulates the dead‐time under universal input and full load. With the light load ZVS control scheme, the system can achieve a maximum efficiency of 94.12 and 80.23% in the worst case. The prototyped converter can achieve power density (exclude case and controller) of 18 W/in3. [ABSTRACT FROM AUTHOR]

In this work, a seven‐level switched capacitor boost inverter (7L‐SCBI) is proposed with minimal resource count. The proposed inverter requires only eight switches and two capacitors to generate a seven‐level voltage. The proposed 7L‐SCBI is capable of generating a multilevel voltage as well as boost the input DC‐link voltage up to 1.5 times with a reduced blocking voltage of switches and capacitors. The comparison in terms of efficiency and device count with other switched capacitor topologies is presented in detail. The performance validation of the proposed 7L‐SCBI is done with the help of a laboratory prototype. [ABSTRACT FROM AUTHOR]

The major issue with the three‐level active neutral point clamped (ANPC) inverter has been the requirement of a higher DC‐link voltage with a lower peak of the output voltage. In this study, a new unity gain ANPC multilevel inverter topology has been proposed with a lower number of switches. The proposed topology generates a nine‐level output voltage with a single DC voltage source, four capacitors, and ten switches. The two floating capacitors have a voltage rating of 0.25Vdc which reduces the overall cost and improves the efficiency of the topology. The performance of the proposed topology has been demonstrated using various comparisons and experimental results. [ABSTRACT FROM AUTHOR]

Development of charging infrastructure is one of the key factors for the successful operation of electric vehicles. This study proposes a power converter for on‐board electric vehicle battery charger suitable with universal input voltage (85–265 V). The proposed converter is able to make better power quality by the reduction in total harmonic distortion (THD) of supply current, power factor correction and accurate output voltage regulation. System configuration includes diode bridge rectifier followed by three‐level DC–DC SEPIC converter which emphasises on the reduction of voltage stress and switching loss across switches, thereby reduces the switch rating and improves the overall efficiency of the converter. The converter employs a duty cycle feed‐forward controller scheme for charging the battery at constant voltage (CV) and constant current (CC) mode. Incorporating the above‐said controller scheme has benefits of low THD in supply current, make power factor unity and nearly no zero‐crossing detection. The proposed power factor correction converter system analysis is executed in continuous conduction mode. The system performance is evaluated with 400 V, 48 AH battery charging under CV and CC mode through MATLAB/Simulink and experimentation. To estimate the features of power quality indices like power factor and THD is recorded under the wide range of supply variations. [ABSTRACT FROM AUTHOR]

In this study, a wide load range zero‐voltage zero‐current switching (ZVZCS) dual‐active‐bridge DC–DC converter using auxiliary parallel networks is proposed. The outstanding feature of the proposed converter is that all of the switches are allowed to operate with zero‐voltage switching while four of the switches are allowed to operate with zero‐current switching, due to the use of two auxiliary parallel networks, which were paralleled to two active bridges, respectively. Furthermore, the circulating current losses can be reduced significantly by using unified boundary trapezoidal modulation method. Based on these merits, the proposed converter has some advantages for the wide range load variation applications with less circulating current losses. The operation principles, soft‐switching conditions and loss analyses comparison are given in this study. These benefits and characteristics mentioned above are verified from the experimental results by using a 1 kW prototype. [ABSTRACT FROM AUTHOR]

This study proposes the generalised analysis of the interleaved zero-voltage-switching (ZVS) boost-flyback converter containing a number k of interleaving cells. The analysis provides a general description of the energy transfer process of the circuit and yields a systematic approach for the adequate converter design. The effect of the leakage inductance on the voltage gain is verified in detail, enabling the designer to deal with the trade-off between high step-up operation and soft-switching occurrence. In addition, the conditions to guarantee ZVS for all switches are investigated, providing the basis for the adequate choice of the auxiliary switching capacitance and dead time. Experimental results obtained from the testing of a 500 W, 100 kHz, 96.9% peak efficiency prototype validate the analysis carried out and the proposed design procedure for the converter. [ABSTRACT FROM AUTHOR]

High step-up, high-efficiency and cost-effective dc–dc converters with high power density, as an interface to boost the low voltage of alternative sources to the utility voltage level, are an important part of renewable energy systems. In this study, a novel high step-up converter is proposed with a switched-capacitor. By introducing the switched-capacitor unit in the converter, the voltage of the switched-capacitor is coupled into the charging circuit of the input filter-inductor. Thus, the boost factor can be enlarged up to (1 − 2D) and the problem of the inrush current can be avoided due to the filter inductor. By replacing the filter inductor with the voltage multiplier unit, the boost coefficient of one coupled inductor voltage multiplier is increased to 2n and the voltage stress of the power switch is significantly reduced. Moreover, the energy of the leakage inductor is recycled by the switched-capacitor with the reduction of the voltage spike and the switches' stress. The working principle and the steady-state characteristics are analysed in detail in this study, and a comparison is made between the proposed converter and other high step-up converters. The experimental results based on a 200 W 20 to 200 V prototype verify the correctness and the feasibility. [ABSTRACT FROM AUTHOR]

This study presents a hybrid resonant three‐level (TL) zero‐current‐switching (ZCS) converter for distributed photovoltaic power applications accessing medium‐voltage DC (MVDC) distribution network. The main constituents of the converter is a neutral point clamped TL circuit, an auxiliary circuit along with two transformers and six switches. The ZCS condition of the TL circuit is reached by operating the auxiliary circuit utilising pulse width modulation technique. It delivers the majority of the power and the switching loss is remarkably reduced. A section on the influence of the turn's ratio of the auxiliary transformer on the current is also presented. The piecewise linear electrical circuit simulation simulation results validate the designed parameter principles. For the sake of comparison, an experimental prototype is developed of 300–1500 V/1500 W to validate the performance of the proposed converter. [ABSTRACT FROM AUTHOR]

In this study, a new zero voltage switching (ZVS) synchronous buck converter with ultra-high step-down conversion ratio is introduced. By combining coupled inductors and energy-transferring capacitors, operating duty cycle is significantly extended while the voltage stress across the switches is reduced. Thereby, extremely low voltage gain can be achieved and the conduction loss is reduced owing to using switches with lower voltage rating. Also, by applying the interleaved method and complementary pulses for switches, the current stress and the output current ripple are reduced. In the proposed converter, soft switching condition is achieved for all switches without any auxiliary circuit. As a result, the overall efficiency of the introduced converter is improved. The converter operation and its design considerations are discussed. Experimental results are presented to validate the theoretical analysis. [ABSTRACT FROM AUTHOR]

The seven-level (7L) inverter with a nearly sinusoidal output voltage is suitable for renewable energy conversion applications. A novel 7L inverter topology with switched capacitors is proposed here. The topology is composed of an active clamping inverter and a switched-capacitor part in series connection. The switched-capacitor part, consisting of three switches and two clamped capacitors, can provide 1/3 or 2/3 level of output voltage. By connecting switched-capacitor part in forward or backward series to the inverter output, a 7L output voltage waveform can be obtained with enough redundancy switching states to balance the voltage of switching capacitors. A modified modulation method is also proposed to make the topology operating properly. The voltage of switched-capacitor part can be sustained E and 2E alternately by adjusting a modulation index according to the capacitor voltage and load current. The effectiveness of the proposed topology is validated by both simulative and experimental results. Comparing with conventional 7L inverter topology, less number of devices were adopted in the proposed topology with a simple and practicable modulation method. [ABSTRACT FROM AUTHOR]

This study presents low‐power sample and hold (S/H) circuits using second‐generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low‐power consumption, high‐speed and absent from non‐overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single‐ended S/H, differential S/H and serial‐to‐parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 µm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures. [ABSTRACT FROM AUTHOR]

Recently, diverse technologies and apparatus are launched to enhance service reliability in the distribution level. In this regard, remote controlled switches (RCSs) can play a prominent role in declining interruption durations and costs. The stochastic nature of contingencies, however, imposes considerable uncertainty on the achievements of RCS deployment. This study presents a model to consider the financial risk induced by the uncertainty in an RCS placement problem. The risk awareness of distribution companies is scrutinised through an effective risk measure, i.e. conditional value at risk. In the model, the number and location of RCSs are determined such that the system expected cost is minimised and the risk is managed. The model is treated as a multi‐objective problem with two conflicting objectives. The problem is then solved via a non‐dominated sorting genetic algorithm II. This algorithm results in a set of non‐dominated solutions. Finally, a fuzzy decision making method is applied to select the best placement strategy from the set. The presented model is applied on RBTS‐Bus4, where the findings reveal the importance of considering the risk in an RCS placement problem as well as the capability of the method in doing so. [ABSTRACT FROM AUTHOR]

Distribution system reliability is directly affected by the placement of various types of protective devices at different locations of the distribution system. To reduce the momentary interruptions, fuse‐blow scheme is used which in turn increases sustained interruption. Utilities having more concern to the sustained interruptions prefer to use fuse‐save scheme over fuse‐blow scheme. Different models have been developed to solve the problems incorporating placement of various combinations of protective devices in a distribution network for increasing the profit of the utility. The uncertainties in temporary failure rates, permanent failure rates, repair rates and load data have been considered in the problem formulation using three‐point estimate method. A generalised objective function capable of simulating different combinations of the protective devices has also been developed. The formulated problems have been solved for 58 bus and IEEE 123 bus distribution networks using mixed integer non‐linear programming optimisation technique. After analysing the test results of the various scenarios for the two test systems, it is concluded that maximum profit for the utility is obtained by using the scenario corresponding to a combination of the four protective devices, namely reclosers, switches, fuse‐blow fuses and fuse‐save fuses. [ABSTRACT FROM AUTHOR]

This study presents a new multilevel inverter (MLI) with reduced devices, for low/medium‐ and high‐voltage applications. The proposed MLI is evolved from existing cross‐connected source‐based multilevel inverter (CCS‐MLI), results in reduced switches, driver circuits, diodes, and DC voltage sources when compared with the classical CHB, CCS‐MLI, and other MLIs. Owing to reduced device numbers, the complexity, size, cost, and maintenance of the proposed topology are greatly reduced. The detailed analysis and working of the proposed topology is presented along with its comparison with classical, CCS‐MLI, and other MLIs. Different algorithms are presented for selecting appropriate magnitudes of DC voltage sources to generate different voltage levels in the output. The proposed MLI is suitable for grid integration of renewable energy sources. The concept is presented through modelling and simulation in MATLAB/Simulation environment and validated through real‐time simulator OPAL‐RT (OP‐4500). [ABSTRACT FROM AUTHOR]

Owing to the key role of the power electronic converters in various applications, their reliability is an important issue. The electrolytic capacitor and the power switch are the most vulnerable components of the converters. On fault occurrence in these components, a suitable remedial strategy should be employed to prevent further damages. The first step in any remedial strategy is fault diagnosis including fault detection and identification. This study proposes a technique for switch fault diagnosis and capacitor lifetime monitoring in non‐isolated single‐switch DC–DC converters. The proposed cost‐effective method could be easily implemented using a printed circuit board Rogowski coil (PCBRC) on the capacitor terminals. The derivative of the capacitor current is captured by the PCBRC. The captured signal contains suitable signatures for detection of switch open‐circuit and short‐circuit faults. In addition to switch fault detection, lifetime of the converter capacitor is also monitored by the PCBRC via calculation of the capacitor equivalent series resistance. The proposed technique is implemented for a buck converter. The experimental results confirm the capability of the proposed technique for switch fault diagnosis and capacitor lifetime monitoring in non‐isolated single‐switch DC–DC converters. [ABSTRACT FROM AUTHOR]

Software defined networking (SDN) is an emerging networking architectural framework which aims to provide the complete separation of data forwarding plane and control plane. The two main benefits of SDN are lower cost and improved management. OpenFlow is a well‐known architecture that facilitates SDN. The core idea of OpenFlow is to control the switches or routers through programming from the centralised controller. The connection reliability is a major concern for network service providers to meet quality of service requirements. Hence, an investigation of network resiliency is required for this new paradigm. The resiliency is the network's ability to survive against attacks and other component failures. This study investigates and compares different data forwarding algorithms currently supported by the POX OpenFlow controller standards for network protection and restoration. A thorough investigation of existing approaches or standards in SDN not only is essential for the research community to better understand the topic, but also plays a crucial role in realising or improving network resiliency or protection and restoration in practice. The authors also provide the extension of one of the components in POX for improvement. The restoration scheme in the current POX components as well as in the modified component is evaluated and compared. [ABSTRACT FROM AUTHOR]

The synchronous buck converter (SBC) with traditional pulse‐width modulation has several disadvantages, such as poor efficiency at light loads. Therefore, this study proposes a new control technique for the SBC that allows power switches to operate with quasi‐resonant valley switching in light load conditions. The voltage ripple produced during the capacitor charging and discharging processes is utilised to simulate an inductor current ripple, and thus the zero position of the inductor current can be emulated without requiring a current sensor. The technique has several advantages, including easily built‐in integrated circuits. A 5‐V/25‐W SBC laboratory prototype was implemented to verify the feasibility of the proposed technology and control scheme, and the experimental findings were satisfactory. [ABSTRACT FROM AUTHOR]

The presence of voltage controlled negative differential resistance was observed in conduction characteristics recorded at room temperature for 300 nm thick spin‐coated films of graphene oxide (GO) sandwiched between indium tin oxide (ITO) substrates and top electrodes of sputtered gold (Au) film. The GO crystallites were found from the X‐ray diffraction studies to have an average size in the order of 7.24 nm and to be preferentially oriented along (001) plane. Raman spectroscopy suggested that the material consisted of multilayer stacks with the defects being located at the edges with an average distance of 1.04 nm apart. UV visible spectroscopy studies suggested that the band gap of the material was 4.3 eV, corresponding to direct transitions. The two‐terminal ITO/GO/Au devices exhibited memristor characteristics with scan‐rate dependent hysteresis, threshold voltage and On/Off ratios. A value of >104 was obtained for On/Off ratio at a scan rate of 400 mVs−1 and 4.2 V. [ABSTRACT FROM AUTHOR]

A single‐switch, single‐stage, three‐phase ac–dc buck–boost converter suitable for medium‐voltage applications is proposed. Basic relations that govern steady‐state converter operation are established, confirmed using PSCAD/EMTDC simulations, and substantiated experimentally. Simulation and experimental results establish that the proposed converter has good dynamic performance in buck and boost modes, with near unity input power factor. [ABSTRACT FROM AUTHOR]

In this study, AC characterisation of DNA molecular wires, effects of frequency, temperature and UV irradiation on their conductivity is presented. λ‐DNA molecular wires suspended between high aspect‐ratio electrodes exhibit highly frequency‐dependent conductivity that approaches metal‐like behaviour at high frequencies (∼MHz). Detailed temperature dependence experiments were performed that traced the impedance response of λ‐DNA until its denaturation. UV irradiation experiments where conductivity was lost at higher and longer UV exposures helped to establish that it is indeed λ‐DNA molecular wires that generate conductivity. The subsequent renaturation of λ‐DNA resulted in the recovery of current conduction, providing yet another proof of the conducting DNA molecular wire bridge. The temperature results also revealed hysteretic and bi‐modal impedance responses that could make DNA a candidate for nanoelectronics components like thermal transistors and switches. Further, these experiments shed light on the charge transfer mechanism in DNA. At higher temperatures, the expected increase in thermal‐induced charge hopping may account for the decrease in impedance supporting the 'charge hopping mechanism' theory. UV light, on the other hand, causes damage to GC base‐pairs and phosphate groups reducing the path available both for hopping and short‐range tunneling mechanisms, and hence increasing impedance – this again supporting both the 'charge hopping' and 'tunneling' mechanism theories. [ABSTRACT FROM AUTHOR]

In power substations, switching operations of circuit breakers and disconnect switches generate transient electromagnetic emissions, which may interfere with the normal operations of electronic equipments. This study introduces the design of a novel wireless transient measurement system for measuring or monitoring transient electromagnetic emissions in power substations. Unlike traditional transient measurement systems that use several standalone waveform recording equipment, the presented system, adopting novel network measurement concept, works as a truly automatically controlled interactive data acquisition multi‐node network, and has the ability to provide time‐correlated data from numerous sensors. The accuracy of time correlation is smaller than 1.4 μs. As a result, it provides excellent scalability and is well suited for the measurement of analogue signals spread over a large physical space with time synchronisation. Another major difference is that the new system uses wireless links and programmable devices to replace cables and data acquisition equipment of currently available systems, thus making the new measurement system more compact, flexible and much more powerful. The designed measurement units could do both time‐domain measurement and real time spectrum analysis. [ABSTRACT FROM AUTHOR]