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An all-digital sliding-mode (ADSM) controlled dc-dc converter, utilizing single-bit oversampled frequency domain digitizers in its feedback path is proposed. Sliding-mode control provides several benefits over the traditional PID control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. However, analog implementations of sliding-mode control require several amplifiers in the controller and suffer from process, voltage, and temperature variations. In the proposed approach, the sliding-mode controller (SMC) is implemented digitally; utilizing a first order single-bit ΣΔ frequency to digital converter (ΣΔFDC)-based feedback and reference digitizing ADCs, running at 32-MHz sampling rate. The ADSM regulator achieves 1% settling time in less than 5 μs for a load variation of 600 mA. The SMC uses a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady-state error (or dc offset), and band limits the switching frequency, which are the two common problems associated with SMCs. The IC is designed and fabricated on a 0.35-μm CMOS process occupying an active area of 2.72 mm2. [ABSTRACT FROM AUTHOR]

A noise-shaped direct digital IF to RF (DIF2RF) DAC with embedded upconverter mixer is presented. The digital IF signal is noise shaped by a bandpass Σ-Δ modulator with 1-bit IF output followed by a semidigital finite impulse response (FIR) filter. The current mode FIR filter combines scaled values of the local oscillator (LO) signal for performing reconstruction filtering and upconversion in a single module. The DIF2RF design modulates the digital IF signal with a digital LO signal. This topology eliminates the transconductance nonlinearity of conventional mixers and is inherently linear due to single-bit digital IF input. The presented architecture reduces clock jitter sensitivity of 1-bit DACs by masking IF clock transitions with LO signals. A prototype of the DIF2RF DAC is designed and fabricated in a five-layer metal 0.25-μm digital CMOS process. The architecture can be used in low-power software-defined digital-IF transmitters. The DIF2RF DAC consumes 49 mA from a 2.5-V supply, achieving -64.7-dBc third-order intermodulation at 1.03 GHz with a spurious-free dynamic range of 72 dB in a 15-MHz bandwidth. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes the state-of-the-art design approaches to delta-sigma (ΔΣ) frequency synthesizers for wireless transceiver applications. Various synthesizer architectures, including the integer and fractional-N synthesizers, and frequency-to-digital converters (FDC) based digital frequency synthesizers are described. Design specifications for several loop parameters such as noise shaper order in the feedback modulator, loop filter bandwidth, VCO phase noise are based on modulation accuracy and frequency resolution specifications. Advantages of digital loop filter based ΔΣ frequency synthesizers are analyzed. [Copyright &y& Elsevier]

Wideband low-noise ΣΔ fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop non-linear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order ΣΔ modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-μm CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled. [ABSTRACT FROM AUTHOR]