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This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications. [ABSTRACT FROM AUTHOR]

This paper presents a filtering power amplifier (PA) with wide bandwidth. A bandpass filter (BPF) using discriminating coupling is first proposed to be utilized as the output matching network (OMN) of PA. Discriminating coupling means that the fundamental and the harmonics of the proposed structure have different coupling coefficients. Thus, the input impedances of the fundamental, second and third harmonics could meet the requirements of the extended continuous mode theory, respectively. Also, good frequency selectivity is obtained. The working principle of discriminating coupling, the filter synthesis theory and the equivalent circuit are utilized to guide the design of the filtering PA. To demonstrate the proposed structure, a compact filtering PA operating at 1.8 GHz is designed. The measured results exhibit good frequency selectivity and high power added efficiency (PAE). More importantly, comparing to the previous filtering power amplifiers (PAs) with good frequency selectivity, the proposed design possesses wide bandwidth of 31.1% with PAE higher than 60%. [ABSTRACT FROM AUTHOR]

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies $220\times 630\,\,\mu \text{m}^{2}$ and has no power consumption. [ABSTRACT FROM AUTHOR]

This paper analyzes the ability to suppress in-band noise power of a regenerative amplifier (RA) operating in the nonlinear regime in response to a continuous wave (CW) input tone. As opposed to the linear regime where a CW tone and the noise floor experience the same transfer function, it is shown that the non-linear saturation behavior of an RA yields different transfer characteristics between a CW tone and noise, ultimately leading to an improvement in the output carrier-to-noise ratio (CNR). This is all thanks to the high gain, narrow bandwidth, and the compressive third-order nonlinearity of the RA. This non-linear noise suppression is first analyzed mathematically using single tones in the frequency domain to represent the signal and the noise. Then, simulation of an RA circuit model is shown to be in excellent agreement with the analytical results. Lastly, a discrete RA has been implemented to experimentally verify the noise-suppression phenomenon. The measurement results clearly demonstrate noise suppression and show an output CNR improvement of up to 3 dB. Potential applications of the RA with noise suppression are also discussed. [ABSTRACT FROM AUTHOR]

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from $460 \,\mathrm {k\Omega }$ to $300 \,\mathrm {G\Omega }$ allowing the TIA to process dc currents with a dynamic range of more than $100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between $0.3 \,\mathrm {M\Omega }$ and $100 \,\mathrm {M\Omega }$ , resulting in an overall ac transimpedance between $3 \,\mathrm {M\Omega }$ and $1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of $10 \,\mathrm {MHz}$ is achieved. The TIA provides a minimum input-referred current noise density of $1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of $1.5\,\mathrm {V_{pp}}$ with a THD below $1 \mathrm {\%}$ on a $1.8-\mathrm {V}$ supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions. [ABSTRACT FROM AUTHOR]

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- $\Omega $ load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs. [ABSTRACT FROM AUTHOR]

Walsh-Hadamard based orthogonal sampling of signals is studied in this paper, and an application of this technique is presented. Using orthogonal sampling, a single analog-to-digital converter (ADC) only is sufficient to perform parallel (simultaneous) recording from the sensors. Furthermore, employing Walsh functions as modulation signals, the required bandwidth of the ADC in the proposed system is equal to the bandwidth of a time-multiplexed ADC in a system with identical number of recording channels. Therefore, the bandwidth of the ADC in the proposed system is effectively employed and shared among all the channels. The efficient usage of the ADC bandwidth leads to saving power at the ADC stage and reducing the data-rate of the output signal compared to state-of-the-art recording systems based on frequency-division multiplexing. This paper presents the orthogonal sampling technique for neural recording in multi-channel recording systems which is implemented with four recording channels using a $0.18~\mu \text{m}$ technology which results in a power consumption of $1.26~\mu \text{W}$ /channel at a 0.8 V supply. [ABSTRACT FROM AUTHOR]

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account. [ABSTRACT FROM AUTHOR]

This paper presents a time-interleaved analog-to-digital converter mismatch calibration, which can be adapted to any interleaving factor and calibrate offset, gain, time skew and bandwidth mismatches. Moreover, the proposed scheme utilizes a non-return-to-zero pilot signal, avoiding the high-resolution requirements of sinusoidal generators. In addition, there are no multiplications in the detection path in contrast with the state-of-the-art approaches. Consequently, the proposed calibration presents the smallest complexity in terms of hardware requirements compared to previous work (to the author’s knowledge). Therefore, the proposed calibration can be made with the smallest area and power consumption. Numerical simulations show an SNDR improvement of 49.52 dB for a 12-bit 4-channel TI-ADC and an SNDR improvement of 29.64 dB for an 8-bit 32-channel TI-ADC when random mismatches are applied. The measurement results show an SNDR improvement of 24.68 dB for a 3.6 GS/s 2-channel TI-ADC experimental board. [ABSTRACT FROM AUTHOR]

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate $< 1\text{E}$ -10 with a power efficiency of 4.75 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper investigates the secure consensus tracking problem for continuous-time nonlinear multiagent systems with sensor attacks. By designing a secure data selector, the unattacked output data is extracted from a group of output measurements under sparse sensor attacks. Then, by virtue of the obtained data and neural networks, a state observer is constructed to estimate the unavailable system states, where the convex combination theory is introduced to reduce the difficulty of solving observation gains. To utilize the limited communication resources reasonably, a novel saturated threshold event-triggered control strategy is proposed to reduce control updates, and then each update is encoded into a binary signal (0 or 1) to further reduce the occupation of communication bandwidth. The designed control scheme ensures that all closed-loop signals are semi-globally uniformly ultimately bounded, and its effectiveness is verified via a simulation of attitude control of unmanned aerial vehicles. [ABSTRACT FROM AUTHOR]

This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

Digital Storage Oscilloscopes (DSOs) conjugate high performance with large number of features and flexibility. The basic structure, based on fast Analog to Digital Converter (ADC) and memory, is augmented with several components for channel matching and bandwidth improvement, and processors that provide visualization, frequency processing, jitter and stability measurement, etc. Unfortunately, fine resolution in sample rate selection is not available, such that for several applications the user must run complex measurement procedures that require data download and offline processing. The paper proposes a dedicated digital circuit that offers fine control of the time-base by real time downsampling the input stream at an almost arbitrary sampling rate. The proposed circuit implements a series of operations involving real-time data filtering, defragmentation and packing, which are not considered by alternative approaches, like those based on polyphase filters, that offer very limited choices for the sampling rate. The circuit is designed to work in conjunction with the highest performance DSOs that use a multichannel architecture. Design rules for circuit design are provided together with implementation results in 14nm FinFET technology. When designed for an architecture with 64 channels with 8bit input samples the circuit works in real time with a sampling rate of 220 GSps running at 3.42 GHz, with a silicon footprint of 0.17 mm2 and a power dissipation of 0.85W. [ABSTRACT FROM AUTHOR]

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $. In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

This paper presents direct sequence spread spectrum (DS/SS) datalinks operating at 92-100 GHz with spreading factors up to 100K. Unlike traditional DS/SS datalinks which rely on preamble and cyclic dispreading for synchronization, the reported datalink uses a self-synchronous demodulation scheme, avoiding the large hardware complexity associated with exceptionally large spreading factors, and avoiding the difficulties of synchronizing the long de-spreading codes that are applicable to mm-wave systems. A demonstration link chipset is presented operating at 92-100 GHz with a spreading factor of 104K and a spread bandwidth of 6.0 GHz (baseband bandwidth of 56Kb/s) while consuming a total of 425mW. [ABSTRACT FROM AUTHOR]

This paper proposes a technique which allows quadband impedance matching and impedance level shifting Doherty power amplifier (DPA) design. By using novel coupler networks with reactance and choosing appropriate complex load impedances, the quadband DPA can reach a power back-off range (OBO) of over 9 dB. In addition, the peak PA branch and the carrier PA branch use different coupler network parameters in order to satisfy different impedance requirements. To illustrate the design procedure a quadband DPA with 9 dB OBO operating in 0.5-0.7 GHz, 1.5-1.7 GHz, 2.5-2.7 GHz, and 3.5-3.7 GHz frequency ranges is designed, fabricated and tested. Measurements demonstrate that the DPA can deliver saturated output power between 43.1 dBm and 43.8 dBm in all four bands, with a drain efficiency ranging from 63.3% to 66.5%. Also, drain efficiency of from 42.2% to 52.3 % can be obtained at an OBO of 9 dB level. The DPA implemented here shows state-of-the-art performance for OBO under quad-band operation. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of simultaneous fault detection and control (SFDC) for Markov jump systems (MJSs) over sensor networks. In order to save the bandwidth of the network, round-Robin protocol is adopted for the communication between the sensors and fault detection filter. First, to fully utilize the data of sensor networks, a new distributed system is developed especially for SFDC, and a residual system, which integrates the MJSs with the distributed SFDC system, is also established. Then, by constructing a mode-dependent Lyapunov functional, the conditions for distributed SFDC are derived, which can make the residual system asymptotically mean-square stable and meanwhile satisfy the prescribed H∞ performance requirements. Finally, comparison analyses are made by examples to illustrate the effectiveness and superiority of the proposed new design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

Constrained by the transimpedance limit, the conventional 1-stage shunt-feedback transimpedance amplifier (1S-SF-TIA) suffers poor noise and gain at higher data rates. In this paper, we propose to use a multi-stage stagger-tuned amplifier (MSTA) to constitute TIA (MSTA-TIA), which not only transcends the transimpedance limit of 1S-SF-TIA, but also realizes noise reduction in multiple fronts. First, the high-gain MSTA enables 17X TIA gain over 1S-SF-TIA, which effectively suppresses the white noise. Second, the MSTA realizes at least 2.8X~1.6 lower noise than the conventional multi-stage amplifier, which is essential to form low-noise TIA since the amplifier noise usually dominates. Third, the TIA built upon the 3-stage STA also shows steeper out-of-band roll-off to enable high-frequency noise reduction. Overall, the MSTA-TIA achieves 6.9X and 1.9X noise power reduction over conventional single-stage and multi-stage SF-TIAs. As a demonstration, a 10 Gb/s optical receiver front-end prototype employing proposed MSTA-TIA topology is implemented in a standard $0.18~\mu \text{m}$ CMOS technology. It achieves transimpedance gain of 68.3dB $\Omega $ , electrical bandwidth of 8.5GHz, and excellent input-referred noise current of $0.97~\mu $ Arms. The chip occupies 0.78 mm2 while consuming 43 mA from 1.8 V power supply. The low-noise design methodology in this paper empowers mature CMOS to compete with SiGe to make low-noise high-gain optical IC. [ABSTRACT FROM AUTHOR]

This paper implements a wide aperture high-resolution true time delay for frequency-uniform beamforming gain in large-scale phased arrays. We propose a baseband discrete-time delay-compensating technique to augment the conventional phase-shift-based analog or hybrid beamformers. A generalized design methodology is first developed to compare delay-compensating analog or hybrid beamforming architecture with their digital counterpart for a given number of antenna elements, modulation bandwidth, ADC dynamic range, and delay resolution. This paper shows that delay-compensating analog or hybrid beamformers are more energy-efficient for high dynamic-range applications compared to true-time-delay digital beamformers. To demonstrate the feasibility of our proposed technique, a four-element analog delay-compensating baseband beamformer in 65-nm CMOS is prototyped. A time-interleaved switched-capacitor array implements the discrete-time delay-compensating beamformer with a wide delay range of 15-ns and 5-ps resolution. Measured power consumption is 47 mW with frequency-uniform array gain over 100-MHz modulated bandwidth, independent of angle of arrival. The proposed delay compensation scheme is scalable to accommodate the delay differences for large antenna arrays with higher range/resolution ENOB compared with prior art. [ABSTRACT FROM AUTHOR]

Clock skew and component mismatches in continuous-time DACs introduce two types of error: static error and dynamic error. Both types of error typically limit the performance of practical, high-resolution, and continuous-time DACs, but most prior calibration techniques primarily reduce only static error. An exception is a recently published mismatch noise cancellation (MNC) technique that adaptively measures and cancels both types of error over the DAC’s first Nyquist band. However, a disadvantage of the technique is that it requires an oversampling ADC that operates at several times the DAC’s Nyquist rate to prevent convergence error that would otherwise be caused by aliasing. This paper presents a sub-sampling version of the MNC technique that avoids this limitation at the expense of a lower calibration convergence rate. As proven in the paper, the subsampling MNC technique allows aliasing to occur, but in such a way that convergence error is avoided. [ABSTRACT FROM AUTHOR]

This paper presents a 2.4–6 GHz highly integrated broadband GaN power amplifier (PA) with three stages for 2.4-/5-GHz dual-band 802.11ax application. A compact external output matching network is introduced to realize broadband output matching, while reducing the loss of the output matching network and saving the chip area. A novel topology of coupled resonators is exploited for the broadband inter-stage matching to cover the 802.11ax bands from 2.4 to 6 GHz. In the proposed topology, the coupling between the primary and secondary resonators is through a series inductor and a series capacitor. Compared with other conventional coupled resonators, the proposed topology produces an additional complex pole, further extending the bandwidth. The PA was designed and fabricated in Wolfspeed 0.25-0.35 μm GaN-on-SiC technology. The implemented PA achieves a saturated output power (Psat) of 35.2–36.3 dBm with a maximum power added efficiency (PAE) of 38–53% from 2.4 to 6 GHz. When tested with an 80-MHz, 256-quadratic-amplitude modulation (QAM) 802.11ax signal, the PA delivers an average output power of 27.1 and 25.7–27.2 dBm with a PAE of 20.9% and 18.4–24.6% in the 2.4-GHz and 5-GHz wireless local area network (WLAN) bands, respectively, while meeting the specification of error vector magnitude (EVM) below −32 dB. [ABSTRACT FROM AUTHOR]

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP1dB of 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP1dB of up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP1dB of up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm2 chip area including test pads. To the best of the authors’ knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process. [ABSTRACT FROM AUTHOR]

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35 μm CMOS process and occupies an active chip area of 456 × 278 μm2. Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054 μs response time. The power-supply rejection (PSR) at 100kHz is −75.6dB. [ABSTRACT FROM AUTHOR]

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in the environment. The building blocks of the sensor nodes comprise a transmitter, a wake-up receiver, and a ranging receiver, all implemented in a 65 nm CMOS technology. The transmitter includes two switched-capacitor converters and an output multiplexer to generate a four-level driving signal and broadcast either a wake-up sequence or a digitally synthesized ultrasound Chirp. The transmitter dissipates $0.43~\mu \text{J}$ and ${0.82~\mu \text {J}}$ to broadcast the wake-up signal and the Chirp, respectively. A mixer first architecture is exploited in the wake-up receiver to reduce the always-on power consumption of the nodes. The ranging receiver uses a heterodyne architecture suited for the FMCW. The power consumption of the wake-up receiver and ranging receiver is 23.6 nW and $0.56~\mu \text{W}$ , respectively. The proposed rangefinder is experimentally characterized up to a 1 m distance in air and dissipates $1.25~\mu \text {J}$ per measurement, achieving a resolution of 18.7 mm at 0.55 m. [ABSTRACT FROM AUTHOR]

In the transmit signal path of a cellular terminal that supports the Long-Term Evolution (LTE) standard, the third-order counter-intermodulation (CIM3) product can be a significant contributor to spurious emissions in protected bands, primarily in cases where all the transmit power is concentrated in one resource block at the edge of the allocated bandwidth. This problem can be addressed with a harmonic rejection architecture for the up-conversion mixer in the transceiver. Prior work in this area retains the four-phase baseband inputs of a conventional quadrature mixer, utilizes various techniques in the local oscillator (LO) path involving overlapping LO waveforms to suppress harmonics and requires the digitally-controlled oscillator (DCO) to be operated at two or more times the LO frequency. The harmonic rejection architecture presented in this paper has six baseband phases and six non-overlapping LO phases and, for higher-frequency bands, allows the DCO to run at 1.5 times the LO frequency. It also provides an inherently higher uncalibrated image rejection than architectures with quadrature baseband inputs, which is advantageous for any wireless communication standard that supports higher-order quadrature amplitude modulation (QAM) schemes such as 1024-QAM and 4096-QAM. [ABSTRACT FROM AUTHOR]

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain amplifier, and anti-aliasing filter. Because of the miniaturized size of isolation components, this approach can be packaged in chip for industrial applications. This solution replaces the need of bulky/frequency dependent current transformers, complex isolation amplifiers with embedded analog to digital converters, and allows proposed sensors to be used in voltage and current sensing applications. The introduced prototype achieves an input referred offset of 1 mV, 50 dB full-scale signal-to-noise ratio in a 10 kHz bandwidth, and spurious-free dynamic range of 53 dB, while satisfying continuous isolation working voltage of 550 V. [ABSTRACT FROM AUTHOR]

This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band and out-of-band phase-noise. The proposed circuit consists of two, or more, standard loops coupled via an additional phase detector. It will be demonstrated that in this architecture the impact of the main PLL noise sources, the oscillator and the reference buffer, is efficiently traded with the power dissipation without resorting to lossy and area-consuming passive coupling networks. The work then shows how to derive the set of design parameters that grant the desired performance for a given case study. The entire procedure is verified by simulations. [ABSTRACT FROM AUTHOR]

A design methodology for making magnetic coupling wireless power transfer (MC-WPT) systems resonate at given frequencies is proposed in this paper. Proposing such a method not only can improve the energy efficiency against frequency splitting, but also can satisfy the requirement of frequency standards and then promote its industrial application. The method is based on eigenvalues configuration and comprehensively considers all electric parameters. The quantitative relationship between the performance indexes and electric parameters is derived, based on which the expected electric parameters can be quickly and accurately determined. The design theory and design flow are provided, and practical systems are designed, simulated and measured to show the effectiveness of the proposed method. The results show that the proposed method can: 1) eliminate frequency splitting to make MC-WPT systems resonate at a given frequency; 2) utilize frequency splitting to make MC-WPT systems resonate at two given frequencies. [ABSTRACT FROM AUTHOR]

This paper proposes a method that employs novel hybrid continuous class-EFJ power amplifiers (PAs) as carrier PA to design a broadband high-efficiency Doherty power amplifier (DPA). Bandwidth characteristic of the proposed DPA is analyzed in detail. By proper selection of related parameter values, up to 78% fabrication bandwidth can be obtained. Post-harmonic tuning network is applied to improve the bandwidth and enhance the efficiency. Then, a closed design process is presented to design broadband DPA based on derived theories. For validation, a broadband DPA operating in 1.2-2.8 GHz is designed and fabricated. Measurements illustrate that the DPA can deliver saturated output power between 43.7 dBm and 44.1 dBm in 1.2-2.8 GHz, and the saturated drain efficiency from 60.5% to 74.2 % is achieved. Moreover, drain efficiency is 48.1%-57.6% at the 6 dB power back-off. Compared with conventional DPAs, the proposed DPA exhibits superior performance of bandwidth characteristics and power back-off efficiency over a wide bandwidth. [ABSTRACT FROM AUTHOR]

This paper introduces a new class of ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2–22 MHz continuous-time Butterworth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2–8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of −40 °C to 85 °C and supply voltage range of 0.9–1.2 V. [ABSTRACT FROM AUTHOR]

In this paper, a new effective approach is proposed to design compact multifunctional reconfigurable filtering power divider (FPD) based on a developed tunable multi-mode FPD topology. Different from conventional tunable FPD method by cascading tunable filter with power divider (PD), and double tunable filtering structures based on the tunable FPD method, it provides one promising solution of high operation performance, miniaturization and design flexibility enhancement etc., for industrial multi-functional modern wireless communication systems. By reformulating the traditional coupling matrix in terms of element-variable coupling coefficients for the developed tunable FPD topology, bandwidth (BW), center frequency (CF), as well as power division ratio (PDR) tuning are well accounted, which can help guide a new class of tunable FPD designs. For demonstration, a new second-order tunable FPD with only one common ring loaded coupled line tunable resonant unit is implemented as an example without losing generality. Higher-order tunable FPD case is further discussed and investigated by freely generalizing the FPD structure through the adoption of different tunable resonant units without dramatically increasing circuit complexity and size. Experimental results indicates that an improved performance (wider tuning range for CF, BW and PDR with nice isolation and matching), a very compact size and flexible design are achieved in the proposed work, which stands out from those in the literature. [ABSTRACT FROM AUTHOR]

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is < 7mV with roughly 2.5mV due to ESR resistance. The LDO achieves FOM $_{\mathbf {V}}=1$ mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm2. [ABSTRACT FROM AUTHOR]

A novel all-digital phase-locked loop (ADPLL) for fast and high-linear FMCW signal generation is presented in this paper. Fast chirp slope is enabled by two-point modulation (TPM) technique and ramp linearity distortion induced by digitally- controlled oscillator (DCO) is suppressed by wide loop bandwidth. A calibration-free retiming fractional frequency dividing (FFD) scheme based on digital phase interpolator (DPI) is proposed to suppress the $\Delta \Sigma $ quantization noise and break the loop bandwidth limitation. A parasitic insensitive DPI is utilized in the retiming FFD scheme to achieve high-linear phase interpolation. A high frequency resolution DCO with 9.8-kHz/bit least significant bit (LSB) and a vernier time-to-digital convertor (TDC) with 2.3-ps time resolution are employed to further minimize the quantization noise. Implemented in 40-nm CMOS, the ADPLL prototype consumes 33.8 mW power and 0.32 mm2 chip area. Measurement results show that 78 MHz/ $\mu \text{s}$ maximum chirp slope is achieved with 167 kHz root-mean-square (RMS) frequency error. The minimum RMS frequency error is only 5.6 kHz when 300 MHz frequency is swept in 1 ms. The phase noise from 12.15 GHz carrier is −113.6 dBc/Hz at 1-MHz offset. [ABSTRACT FROM AUTHOR]

In this paper, we present a design technique for broadband fully integrated GaN power amplifiers (PAs), with merged bandpass filter (BPF) and AM-PM compensation. The minimum-inductance BPF structure is used as the output matching network of the PA. A new theory of the minimum-inductance BPF is developed and it is shown that, compared to the standard BPF, it can be implemented using lower total inductance and provide higher out-of-band attenuation. Furthermore, using a two-transistor architecture, an AM-PM compensation technique is proposed where compressive and expansive nonlinearity profiles of the transistors’ transconductance and gate-source capacitance are combined to achieve a linear total transconductance and input capacitance, over a wide power range. A fully integrated PA prototype, implemented in a 0.25- $\mu \text{m}$ GaN-on-SiC process with 28-V supply, provides 35.1–38.9dBm output power, 45–61% drain efficiency (DE), 40–55% power-added efficiency (PAE), and 11.3–13.4dB power gain, across 2.0–4.0GHz. For a 256-QAM signal with 7.2-dB PAPR and 100-MHz bandwidth at 2.4GHz, it achieves 2.5% (−32.0dB) rms error vector magnitude (EVM $_{{\mathrm {rms}}}$) and −37.5/−37.6dBc adjacent channel leakage ratio (ACLR), while average output power and DE/PAE are respectively 30.1dBm and 20.6/19.5%, without predistortion. EVM $_{{\mathrm {rms}}}$ and ACLR can be improved to 0.5% (−46dB) and −46.4/−46.8dBc by using digital predistortion (DPD). [ABSTRACT FROM AUTHOR]

This paper presents a novel CMOS peak detect and hold (PDH) circuit scheme for pulsed time of flight (ToF) Lidar application. The proposed PDH circuit, which is one part of analog front end (AFE) circuit of Lidar receiver, is used to widen the narrow input pulse width, aiming to easily digitize the pulse amplitude through a low-speed and low-cost ADC in pulsed ToF Lidar application. The reset voltage clamped to the common-mode level of the input pulse voltage is beneficial to reduce the pedestal error voltage. Meanwhile, the auto-adjust charging current scheme is employed to decrease the peak error through rejecting the overshoot voltage in the proposed PDH circuit. The circuit was implemented and fabricated in a 65-nm CMOS technology. The proposed PDH circuit can detect the pulse voltage with a pulse amplitude range from ~20 mV to ~500 mV and a minimum pulse width of 5 ns. The measured results show that the maximum absolute and relative errors are less than 16 mV and 4.5%, respectively. The layout area of the proposed PDH circuit is equal to $0.17\times 0.14$ mm2. [ABSTRACT FROM AUTHOR]

This paper presents a high sensitivity and dynamic range 25 Gbaud optical receiver including the CMOS transimpedance amplifier (TIA) and Ge-on-Si photodetector. In the TIA with a DC bypassing path, instead of deploying a voltage-controlled path with a fixed feedback strength, a current-controlled path with $g_{\mathrm {m}}$ -adjusting ability is proposed to minimize the noise amplified by the feedback loop and achieve high sensitivity. In addition, in the optical part, a Ge-on-Si photodetector with cube-shape Ge is proposed to boost the responsivity, which therefore overcomes the noise contribution from the TIA and enhance the overall sensitivity of the cascaded optical receiver. The CMOS transimpedance amplifier includes a 3-stage transimpedance pre-amplifier, a 4-stage post amplifier, a CML buffer stage and a DC offset cancellation block. Measurement results show a transimpedance of 66–71 dB $\Omega $ , a SDD21 bandwidth of 18.5 GHz, an input-referred noise current density of 11.1 pA/ $\surd $ Hz, a BER of $1\times 10^{-{12}}$ @ $26~\mu \text{A}$ and a power consumption of 105 mW. The FOM is 5.2 which is the lowest, to the best of the authors’ knowledge. The photodetector achieves a responsivity of 0.57 A/W at 1550 nm and a bandwidth of 40 GHz. The optical receiver achieves an optical sensitivity of −11.7 dBm. Compared with the prior arts, the proposed receiver demonstrates distinct sensitivity and FOM enhancement. [ABSTRACT FROM AUTHOR]

Emerging wireless communication services require the efficient use of available spectrum and improved co-existence of different standards placed in adjacent frequency bands. Co-existence with leakage from primary users in adjacent channels, which falls in the band of interest, is a primary concern for existing and emerging technologies. In this paper, a mixed signal IC technique based on direct sequence spread spectrum is proposed to improve co-existence of radar systems with commercial wireless communication systems. A sinusoid-like pseudo-random sequence is introduced to reduce leakage from radar systems into adjacent channels. The proposed approach reduces the radar signal leakage on adjacent channels by about 22dB when compared with the conventional binary pseudo-random sequence. The proposed technique randomizes narrow and wideband systematic in-band interference, after which interference power can be effectively attenuated through averaging techniques. Experimental results from a 40nm CMOS technology modulator/demodulator prototype demonstrates the feasibility of the proposed architecture. The modulator and demodulator system requires a silicon area of 0.0459mm2 and consumes 4.33mW in total. [ABSTRACT FROM AUTHOR]

This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: an SSDA MMIC with 7.1dB average gain and 200GHz bandwidth; and the world’s first M-SSDA, which has a 12dB average gain and 170GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date. [ABSTRACT FROM AUTHOR]

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%. [ABSTRACT FROM AUTHOR]

In this paper, we show that amplitude transitions that are inherent to the multilevel outphasing radio transmitter architecture distort the transmitted signal due to time-domain discontinuities. In order to address this challenge, we propose a new transmitter architecture called tri-phasing which avoids discontinuities in signal waveforms and thus achieves significantly better linearity than multilevel outphasing. The output waveform in tri-phasing can be made continuous by representing the baseband signal with three components. One of the three components is amplified by discrete amplitude steps, whereas the other two are used to compensate the instantaneous shift in the output waveform due to the discrete amplitude step and to provide fine amplitude resolution. An implementation of the tri-phasing transmitter requires three phase modulators and additional digital signal processing. The system-level simulations performed in this paper demonstrate that the ACLR of a multilevel outphasing transmitter with 4 amplitude levels and 10-bit phase resolution is limited to −48 dBc, when simulated with a 100 MHz carrier-aggregated LTE downlink signal at 2.46 GHz carrier frequency. The proposed tri-phasing transmitter achieves −58 dBc ACLR with the same simulation parameters, indicating that continuous amplitude transitions can significantly improve the transmitter linearity. [ABSTRACT FROM AUTHOR]

A 5-13.5 Gbps multi-standard I/O link receiver is presented in this paper. An inductor-free CTLE, whose gain and bandwidth are highly adjustable, is achieved by using the second-order negative capacitance circuit. A high jitter tolerance clock and data recovery (HJTOL-CDR) is proposed for Spread Spectrum Clock applications. In this work, the JTOL is improved by two ways: first, a partial-noise-shaping-based digital loop filter (PNS-DLF) is implemented to reduce the output jitter caused by the truncation error in the integral path; second, the proposed CDR logic is fully custom designed to operate at a quarter-rate clock of 5 GHz. Moreover, the CDR bandwidth can be tuned to satisfy various data rates and jitter masks. Post-layout simulation shows that the proposed CTLE can provide wide gain tuning range, the boost gain at 10 GHz is beyond 29 dB and the proposed CDR can tolerate up to 31-kppm frequency offset. The proposed receiver is fabricated in 40-nm CMOS with an active area of 0.06 mm2 and 65 mW power consumption at 20 Gbps from 1.2-V supply. Measurement results show that, when receiving the PRBS31 data at 10 Gbps with 5-kppm frequency offset across a channel with 14-dB loss, the JTOL is 0.39 UIpp at 10 MHz and can guarantee a 0.34 UIpp at high frequency, which proves that the proposed receiver can meet stringent standards such as PCIe 3.0/4.0, USB 3.2, DisplayPort 1.4. [ABSTRACT FROM AUTHOR]

This paper presents a wideband and highly linear transimpedance amplifier (TIA) with a high-speed, current-efficient transconductance amplifier and multi-order filtering. The proposed TIA employs a Rauch biquad structure and incorporates an operational transconductance amplifier with an improved feedforward frequency compensation in a nested configuration. The Rauch biquad TIA architecture improves the out-of-band (OOB) selectivity, achieving a high OOB IIP3 of the TIA. The proposed feedforward compensation scheme is effective only at high frequencies and thus further enhances the gain bandwidth product of the transconductance amplifier. The current re-use technique improves the power efficiency of the feedforward stage. The prototype circuit was designed in the TSMC 65nm CMOS technology. The TIA achieves a bandwidth of 80 MHz and an OOB IIP3 of 26.8 dBm with a power consumption of 14.2 mW from a supply of 1.8 V while occupying a core area of 0.037 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we propose O4-DNN, a high-performance FPGA-based architecture for convolutional neural network (CNN) accelerators relying on operation packing and out-of-order (OoO) execution for DSP blocks augmented with LUT-based glue logic. The high-level architecture is comprised of a systolic array of processing elements (PEs), supporting output stationary dataflow. In this architecture, the computational unit of each PE is realized by using a DSP block as well as a small number of LUTs. Given the limited number of DSP blocks in FPGAs, the combination (DSP block and some LUTs) provides more computational power obtainable through each DSP block. The proposed computational unit performs eight convolutional operations on five input operands where one of them is an 8-bit weight and the others are four 8-bit input feature (IF) maps. In addition, to improve the energy efficiency of the proposed computational unit, we present an approximate form of the unit suitable for neural network applications. To reduce the memory bandwidth as well as increase the utilization of the computational units, a data reusing technique based on the weight sharing is also presented. To improve the performance of the proposed computational unit further, an addressing approach for computing the partial sums out-of-order is proposed. The efficacy of the architecture is assessed using two FPGA devices executing four state-of-the-art neural networks. Experimental results show that this architecture leads to, on average (up to), $2.5\times $ ($3.44\times$) higher throughput compared to a baseline structure. In addition, on average (maximum of), 12% (40%) energy efficiency improvement is achievable by employing the O4-DNN compared to the baseline structure. [ABSTRACT FROM AUTHOR]

The integrate and fire converter (IFC) transforms an analog signal into a train of biphasic pulses. The pulse train has information encoded in the timing and polarity of pulses. While it has been shown that any finite bandwidth analog signal can be reconstructed from these pulse trains with an error as small as desired, there is a need for fundamental signal processing techniques to operate directly on pulse trains without signal reconstruction. In this paper, the feasibility of performing online the operations of addition, multiplication, and convolution of analog signals using their pulses train representations is presented. The theoretical framework to perform signal processing with IFC pulse trains imposing minimal restrictions is derived, and algorithms for online implementation of the operators is developed. The performance of the proposed algorithms is studied by quantifying the variations in instantaneous occurrence of pulses. Comparisons are performed with digital processing of reconstructed pulse trains. Moreover, an application of noise subtraction and representation of relevant features of interest in electrocardiogram signal is demonstrated with a sparse data rate of less than 20 IFC pulses per second, and an absolute error in heart rate of 0.16 ± 0.18 bpm. [ABSTRACT FROM AUTHOR]

In this paper, a new method to identify and compensate for the I/Q imbalance in wideband millimeter-wave transmitters using a single undersampling analog-to-digital converter (ADC) is proposed. The proposed method alleviates the need for an I/Q demodulator; hence, simplifying the structure and calibration procedure of the required transmitter-observation receiver (TOR). In addition, an algorithm for estimating the delay and phase offsets between the transmitter and the single-ADC TOR is devised. The presented algorithm improves upon the exhaustive search methods employed in the literature. Measurement results using an off-the-shelf I/Q modulator, driven by an 800 MHz test signal, show about a 5% reduction in the root normalized mean-square error (RNMSE) of its output signal when the proposed method is utilized. Further measurements were conducted to assess the performance of this method, in conjunction with digital predistortion (DPD), when a power amplifier (PA) is added to the transmitter chain. When compared with the application of DPD only, the I/Q imbalance correction allowed additional reductions of about 4% in the RNMSE and 1.5 dB in the adjacent-channel power ratio of the PA output signal. These improvements were obtained with ADC sampling rates as low as 20 times below the Nyquist rate. [ABSTRACT FROM AUTHOR]

With the aggressive scaling of transistor dimensions, intrinsic device gains are dropping but the need for high-gain amplifiers still exists, resulting in a great interest in multi-stage amplifiers. Most existing amplifier topologies rely on Miller capacitors which achieve stability at the expense of reduced speed. In this paper, a new state feedback compensation strategy with gain enhancement using partial positive feedback is proposed whereby a multistage amplifier can be made output-compensated, thereby requiring no Miller capacitance while being able to drive a wide range of load capacitances. After a thorough theoretical analysis, a topology prototype is fabricated in a standard 130 nm CMOS technology and is able to drive loads from 90 nF-50 nF ($\boldsymbol {\sim 555\times }$) using three discrete modes. The amplifier’s power and bandwidth are scalable depending on the expected capacitive load range, with a maximum power consumption of ${\mathrm {185~ \mu \text {W} }}$ from a ${\mathrm {1~ \text {V}}}$ supply. Comparison with state-of-the-art amplifiers shows superior small-signal performance and competitive large-signal performance while driving a significantly larger range of capacitive loads. [ABSTRACT FROM AUTHOR]