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Two important drawbacks of parallel coupled LC quadrature oscillators (P-QOSC) which have not heretofore been addressed thoroughly in the literature are obviated simultaneously in this paper. The first, has to do with the inevitable off-tune operation of the tank which results in quality factor (Q) degradation, and hence, phase noise deterioration. The other, stems from process, voltage, and temperature (PVT) variations which exacerbate quadrature accuracy. Here, a feedback loop is presented which generates a control signal by mixing the quadrature outputs and tunes the injection strength in the coupled oscillators autonomously. A complex coupling factor is implemented which compensates the phase error to prohibit phase noise degradation. The operation of proposed loop is comprehensively studied mathematically. Measurement results of a 0.18 \mu{\text m} CMOS prototype with an active area of 0.5 {\text{mm}}^{2}$ and an overall power consumption of 5 mW corroborate the functionality of the proposed method. Finally, experimental results prove FoM of 185 dB for the core oscillator and a quadrature phase error of less than 0.8^{\circ}. [ABSTRACT FROM PUBLISHER]

Sub-harmonic pulse injection-locked oscillators are becoming attractive candidates for the design of clock multipliers and as building blocks of phase-locked loops. Unfortunately, due to the large amplitude of the injected signals, these circuits cannot be analyzed with conventional methods and very-time-consuming simulations are needed to determine their phase noise performance. Phase-noise simulations are particularly critical when the ratio N between the output and the injection frequency gets large. To address the above issue, this paper provides an efficient computation flow to derive the phase noise of pulse injection-locked oscillators. The flow simply requires the computation of the phase-domain response and the phase noise of the free-running oscillator. An analytical expression, herewith demonstrated and compared against commercial simulation tools, allows calculating the phase noise of the injection-locked oscillator for any frequency ratio N. [ABSTRACT FROM AUTHOR]

In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 \mum standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case. [ABSTRACT FROM PUBLISHER]