Search

This paper presents an analytical solution to characterize harmonic behavior of digitally controlled H-bridge inverter output with two nonlinear effects: sample delay and dead-time. The effect of sampling frequency in uniformly sampled pulse-width modulation (PWM) is discussed, including spectral analysis and compared with the analog modulated PWM. The effect of dead-time on the rising and falling edge of digitized PWM inverter error output is derived in time-domain. The double Fourier integral solution is used to develop the accurate mathematical expressions for the switched output waveforms. The integral solutions are obtained using Jacobi–Anger expansions. The analytical results are verified with simulation using PSCAD and experimental results. [ABSTRACT FROM AUTHOR]

Models of inverters and other converters based on averaging have been widely used in numerous simulation applications. Generalized averaging can be applied to model both average and switching behavior of converters while retaining the faster run times associated with average-value models. Herein, generalized average models for single- and three-phase pulse width modulation inverters are proposed. These models are based on a quasi-Fourier series representation of the switching functions that includes fundamental and switching frequency components as well as sideband components of the switching frequency. The proposed models are demonstrated both in simulation and experimentally and are found to accurately portray both the fundamental and the switching behavior of the inverter. In particular, the use of sideband components allows accurate representation of the variation in switching ripple magnitude that occurs in the steady state. The generalized average models are found to have simulation run times that are significantly faster than those associated with detailed models. Therefore, the proposed generalized average models are suitable for simulation applications in which both accuracy (including the switching behavior) and fast run times are required (e.g., long simulation times, systems with multiple converters, and repeated simulations). [ABSTRACT FROM AUTHOR]

A new gate drive circuit to reduce the power loss and switching noise of single-inductor-multiple-output regulators is presented. Efficiency degradation and switching noise induced by the cross-talk of the voltages and currents within the power stage and buffer are analyzed. A shoot-through-current (STC) controlled buffer with four-transistor (4T) inverters is presented, and the 4T inverter enables internal STC control and generates two outputs with dead-time. To further isolate the cross-talk, two separate high voltage selectors (HVS) with the proposed buffer are used to power the buffer and the power P-MOSFET body, respectively. Simulation results show that the peak and average currents of the proposed buffer are smaller and much less sensitive to the buffer size than those of the traditional inverter based buffer. Two single-inductor-dual-output boost converters with and without the proposed techniques have been fabricated in a 0.35-\mum CMOS process. Experimental results show that the maximum efficiency is increased from 87.8% to 91.6% with the proposed technique. [ABSTRACT FROM PUBLISHER]