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A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series–parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper presents a variable switching point predictive current control (VSP $^2$CC) for the quasi-Z-source inverter (qZSI). The proposed VSP $^2$CC aims to remove the output current error on the ac side, as well as the inductor current and capacitor voltage errors of the quasi-Z-source network on the dc side of the converter. Unlike the previously presented direct model predictive control (MPC) strategies for the qZSI, the proposed control scheme can directly apply the switching signals not only at the discrete time instants, but at any time instant within the sampling interval. Consequently, the shoot-through state can be applied for a shorter time than the sampling interval, resulting in lower output and inductor currents ripples. Experimental results based on field programmable gate array are provided to verify the effectiveness of the introduced control method. As it is shown, the proposed method leads to lower inductor current ripples and less output current total harmonic distortion when compared with the conventional direct MPC. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

To regulate an output ac voltage in inverter systems having wide input dc voltage variation, a buck–boost power conditioning system is preferred. This paper proposes a novel high-efficiency quasi single-stage single-phase buck–boost inverter. The proposed inverter can solve current shoot-through problem and eliminate PWM dead time, which leads to greatly enhanced system reliability. It allows bidirectional power flow and can use MOSFET as switching device without body diode conducting. The reverse recovery issues and related loss of the MOSFET body diode can be eliminated. The use of MOSFET contributes to the reduction of switching and conduction losses. Also, the proposed inverter can be operated with simple pulse width modulation (PWM) control and can be designed at higher switching frequency to reduce the volume of passive components. The detailed experimental results are provided to show the advantages of the proposed inverter. Efficiency measurement shows that using simple PWM control the proposed inverter can obtain peak efficiency of 97.8% for 1.1-kW output power at 30-kHz switching frequency. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulse-width modulation (PWM) scheme for reducing the common-mode voltage (CMV) in the three-phase five-level active neutral-point clamped (5L-ANPC) inverter is proposed, where only the 55 selected voltage vectors among the entire 125 that produce low values of the CMV are utilized. This PWM scheme can significantly reduce the CMV without the increase of switching losses and total harmonic distortion of the output voltages. With the 55 selected voltage vectors, the inverter can still operate up to the maximum modulation index. In addition, the capacitor voltages are controlled by redundant switches of the 5L-ANPC inverters. It has been shown that the peak value of the CMV is decreased to one-twelfth of the dc-link voltage from the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

In this paper, a common grounded Z-source dc–dc converter with high voltage gain is proposed for photovoltaic (PV) applications, which require a relatively high output–input voltage conversion ratio. Compared with the traditional Z-source dc–dc converter, the proposed converter, which employs a conventional Z-source network, can obtain higher voltage gain and provide the common ground for the input and output without any additional components, which results in low cost and small size. Moreover, the proposed converter features low voltage stresses of the switch and diodes. Therefore, the efficiency and reliability of the proposed converter can be improved. The operating principle, parameters design, and comparison with other converters are analyzed. Simulation and experimental results are given to verify the aforementioned characteristics and theoretical analysis of the proposed converter. [ABSTRACT FROM PUBLISHER]

A capacitor voltage-balancing method for a nested neutral point clamped (NNPC) inverter is proposed in this paper. The NNPC inverter is a newly developed four-level voltage-source inverter for medium-voltage applications with properties such as operating over a wide range of voltages (2.4–7.2 kV) without the need for connecting power semiconductor in series and high-quality output voltage. The NNPC topology has two flying capacitors in each leg. In order to ensure that the inverter can operate normally and all switching devices share identical voltage stress, the voltage across each capacitor should be controlled and maintained at one-third of dc bus voltage. The proposed capacitor voltage-balancing method takes advantage of redundancy in phase switching states to control and balance flying capacitor voltages. Simple and effective logic tables are developed for the balancing control. The proposed method is easy to implement and needs very few computations. Moreover, the method is suitable for and easy to integrate with different pulse width modulation schemes. The effectiveness and feasibility of the proposed method is verified by simulation and experiment. [ABSTRACT FROM PUBLISHER]

This paper proposes a new topology for an enhanced-boost Z-source inverter (ZSI) with combined two Z-impedance networks. By two Z-impedance networks and low shoot-through duty cycle, the proposed inverter produces high output voltage gain. In traditional ZSIs for high boosting voltage, a low modulation index is required; hence, under these conditions, the output voltage will have low quality with high total harmonic distortion. Compared with the conventional high-boost ZSI topologies, the proposed inverter uses shorter shoot-through duration and a larger modulation index to improve the output waveform quality. Comparison between the proposed topology and previously proposed schemes, in terms of inductor numbers, voltage and current stresses on elements, sizes of inductors and capacitors, efficiency, and switching device product (SDP) factors of diodes, is made, and the results verify the priority of the proposed topology. The operating principle of the proposed topology is analyzed in detail. Both simulation and experimental results verify the high performance of the proposed inverter. [ABSTRACT FROM PUBLISHER]

Based on the hybrid operation of interleaved flyback micro-inverter in discontinuous and boundary conduction modes (DCM and BCM), a novel adaptive snubber is proposed in this paper. The proposed snubber limits the drain-to-source voltage overshoot of the flyback's main switch during the turn-off process, enabling the use of lower voltage MOSFETs. It also recovers the stored energy in the leakage inductance of the flyback transformer and provides soft switching for the main flyback switch by limiting the rising slope of the MOSFET voltage during the turn-off process resulting in higher efficiency. Exploiting the natural resonant of the flyback converter in BCM, the adopted controller provides ZVS and ZCS for the main switch during the BCM operation. The operation of the flyback micro-inverter with associated controllers is analytically studied, and considerations for an optimum design aiming to higher efficiency are presented. Performance of the flyback micro-inverter with the proposed adaptive snubber and the corresponding controllers is experimentally verified based on a 250W interleaved flyback micro-inverter hardware setup. [ABSTRACT FROM AUTHOR]

This paper introduces a novel pulse width modulation (PWM) technique to eliminate common-mode voltage in odd-multilevel inverters using the three zero common-mode vectors principles. Similarly, as in conventional PWM for multilevel inverters, this PWM can be properly depicted in an active two-level voltage inverter. With the help of two standardized PWM patterns, the characteristics of the PWM process can be fully explored in that active inverter as a switching time diagram and switching state sequence. Due to an unequal number of commutations of three phases in each sampling period, the switching loss is optimized by a proposed current-based mapping algorithm. The switching loss reduction can be up to 25% compared to the same PWM technique with nonoptimized algorithms. The PWM method has been then generalized as an equipotential PWM control, which is valid to both odd- and even-multilevel inverters . The theoretical analysis is verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a new hysteresis current regulation strategy for the neutral point clamped and flying capacitor (FC) three-level inverters. The strategy uses the measured average of the switched phase leg output voltage to adjust the controller hysteresis band as the load back EMF varies to maintain a near constant phase leg switching frequency. The phase leg switchings are then fine tuned to a fixed frequency clock to further improve frequency regulation. Next, the zero-crossings of the measured phase leg average voltages are used to select between positive and negative switched output voltage levels, so that only one hysteresis current regulator is required for the full inverter switched output voltage range. For the FC inverter, a state machine is then added to select between redundant switching states to maintain balanced capacitor voltages. Finally, the controller is extended to a three-phase system by subtracting the common mode interacting current from the total phase leg current error before making any switching decision. The resulting controller achieves a line-to-line harmonic performance that is very close to open-loop phase disposition pulse width modulation, while retaining all of the dynamic benefits of hysteresis current regulation. [ABSTRACT FROM AUTHOR]

This paper presents a novel modulation strategy for a seven-phase three-level inverter, aimed at variable-speed drive applications. Developed space vector pulsewidth modulation (SVPWM) strategy is based on vector space decomposition (VSD) approach and an analysis of multidimensional space vector projections in mutually orthogonal planes. The algorithm represents an extension of a recently developed five-phase three-level SVPWM algorithm and is considerably more complex, due to the existence of three mutually orthogonal planes in a seven-phase system. The difficulties of generalization of space vector strategies, which stem from the nature of the multiphase systems, are highlighted. Increasing the number of phases from five to seven increases the number of switching states from 3 ^5 = 243 to 3^7 = 2187 and the number of orthogonal planes from two to three. This considerably affects the complexity of the offline calculations. However, the final implementation of the algorithm is simple. Developed SVPWM algorithm is compared to an equivalent carrier-based strategy and it is shown that they yield identical performance. The complexity of the algorithms for real-time implementation is compared. Simulation and experimental results, obtained using neutral-point clamped inverter, verify the theoretical developments. [ABSTRACT FROM AUTHOR]

The novel multilevel circuit topologies are proposed in this paper. They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). The topology structure and the operation principle, including the working states’ transitions of the diode-clamped part, the voltages balancing mechanism of the dc link capacitors, and the pulse width modulated carrier control strategy are given. The switched-capacitor circuits contribute not only to balancing the voltages of capacitors but also to boosting the output voltage with a certain input dc voltage. The validity of the MCT-BSD is verified by simulations and experiments. The results show that balancing the voltages of capacitors, boosting the output voltages, and operating under the three-phase condition are all realized effectively in the MCT-BSD. The simulations also show the generalization of the MCT-BSD for n-level topologies. [ABSTRACT FROM AUTHOR]

When small currents are interrupted by a vacuum switch, it is well known that the chopping current and the associated overvoltage are observed. Many investigations on the current-chopping phenomena in alternating-current (ac) circuits have been carried out, but there are no data available on inverter circuits in spite of their recent wide application to synchronous motor systems. In this paper, chopping-current levels and the overvoltages in an inverter circuit under a simple three-level pulsewidth-modulated control are investigated. As a result, the mean chopping-current level is three to four times higher than that in an ac circuit. In particular, high chopping currents occur only when the timing of the current interruption by the vacuum switch synchronizes with that of the inverter's switching, which we call “double chopping.” High chopping current due to double chopping might be harmful since the high overvoltage proportional to the chopping-current level could damage the insulation of electric equipment. However, we experimentally confirmed that a typical surge suppressor could reduce overvoltage. [ABSTRACT FROM AUTHOR]