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This paper proposes an “isolated soft switching current fed LCC-T resonant dc–dc converter for PV/fuel cell applications.” This converter is able to achieve zero voltage switching for front-end inverter switches and zero-current switching for voltage doubler diodes. The majority of dc–dc converters have compact capacitive (C) filter in output, but high harmonic currents through transformer makes them bulky. The proposed converter attempts to improve harmonic content through a transformer under wide load and input variations as well as it can significantly reduce required turns ratio of transformer to achieve required output voltage. For the above reasons, the proposed converter can offer better footprints and therefore it can be a potential candidate for PV/fuel cell applications. This paper presents basic operating principal, detailed analysis, control, and design of the proposed converter with the help of an example. This converter operates in two modes, i.e., constant duty cycle mode and constant frequency mode, depending on load demand, and is explained through operating curves. Finally, experimental results are included for justifying the proposed theory. [ABSTRACT FROM AUTHOR]

A new modular pulsed-power source with fast rise time and step-wise arbitrary output waveform generation is currently under development to drive the Gepulste Elektronenstrahlanlage device investigated at the Institute for Pulsed Power and Microwave Technology (IHM). Acknowledging the complex design procedures necessary to set up a modular pulsed-power source for voltages of up to 120 kV, this paper focuses on the circuit design for a single stage and its validation prior to the generator assembly. Using a semiconductor-based Marx generator topology, the stages are designed to have an output voltage of 1 kV with a pulse current of up to 600 A. When connected to an ohmic load, the measured current rise times are in the order of 46 ns resulting in the current rise rates of up to 10 kA/ $\mu \text{s}$ using the commercial devices. The step-wise arbitrary output waveform is created by generating the switching commands on the stage using a microprocessor and a fast optical synchronization unit. Effective stage shielding is verified by operating the stage in a 100-kV, 2.5-kA electromagnetic interference test bed. This paper presents the design considerations and the corresponding measurements. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

This paper documents a new three-switch, isolated boost dc–dc converter. The major features of the proposed converter are as follows: 1) continuous input current; 2) reduced one active switch, one additional diode, and one additional capacitor; 3) unchanged primary and secondary voltage waveforms of the transformer when the duty cycle is changed; and 4) removal of the snubber circuit. This paper presents the operating principles, analysis, parameter design guidelines, and simulation results for the proposed converter. To verify the performance of the proposed converter, a 400 W prototype was constructed with a 40–60 V dc input. A PID controller was used to maintain the dc output voltage at 400 V. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to control a phase-shifted full-bridge (PSFB) dc/dc converter with variable switching frequency, as a function of the output load power. The main objective of such control is to maximize the conversion efficiency at a wide range of load power levels. By tuning the switching frequency, the net phase of the input impedance of the converter can be manipulated, and thus, at the lower load power operation, the net input impedance can be made highly inductive to achieve zero-voltage switching (ZVS) at the primary-side switches. This paper proposes an efficiency maximization method, which derives an optimum switching frequency based on the load power from a loss-minimization model. In addition, a state-feedback-based control method is proposed for maintaining a tight dynamic regulation over the converter output under a load transient. A 6-kW laboratory prototype of the PSFB converter is developed and designed to validate the proposed control algorithm. The experimental results show a conversion efficiency of 98% at full load and output voltage ripple of ±1%, while ensuring ZVS at all operating points between 100 W and 6 kW. [ABSTRACT FROM AUTHOR]

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless bipolar multistring dc–dc converter based on series-connected submodules. It is intended for converting dc voltage and managing power flow for medium-voltage high-power dc networks. This new converter has a flexible structure of multistrings and each string consists of four valves with their middle points crossly connected through two cost-effect dc capacitors to form power balancing channels between valves. Its transformerless solution and single-stage configuration greatly reduce the converter volume, weight, cost, and power loss. In this paper, voltage ratio range and its influence on submodule design are analyzed. Moreover, a control strategy with focus on current sharing control and submodule capacitor voltage control is proposed. A simulation model rated at ±10 kV 2 MW verifies the feasibility of the proposed dc–dc converter. Experimental results obtained from a 100-V 1.5-kW laboratory setup also confirm the validation of the proposal. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

Many research works have been conducted on increasing the efficiency of interleaved boost converters (IBCs) applied for power factor correction (PFC) by using high-performance power electronic devices and soft switching circuits, which are not helpful in reducing the hardware cost and systematic complexity. In this paper, three intrinsic parameters affecting the efficiency of IBC PFC are found and analyzed, including the switching frequency value, boost inductor value, and output voltage value. Based on the findings, considering the limitations of current ripples, power factor, maximum magnetic flux density, and volume of a boost inductor, an optimization design method for high-efficiency IBC PFC is proposed. A 3.3-kW IBC PFC prototype is developed based on Si devices. The experimental result verifies that the proposed method can improve the efficiency of IBC PFC with low-cost low-performance devices in the full-load range. [ABSTRACT FROM AUTHOR]

The multigap gas switch has been widely used in liner transformer drivers (LTDs), but there is still room for improvement on its self-breakdown and triggering characteristics. In this paper, based on the circuit model of the six-gap gas switch, the gap voltage distribution during the charging and triggering process is analyzed, and the optimization on self-breakdown and triggering characteristics by mounting resistors and capacitors in parallel with switch gaps are theoretically and experimentally investigated. The results indicate that compared with the original switch, when the self-breakdown voltage is about ±90 kV, the standard deviation is reduced from 7.5 to less than 3 kV; for a charging voltage of ±80 kV and by operating at 60% working coefficient, when the negative trigger voltage is 75 kV, the jitter of the switch is reduced from 6.1 to 1.4 ns. [ABSTRACT FROM AUTHOR]

A liquid metal current limiter (LMCL) utilizing a fast switch and a parallel connecting path and consisting of several serial current limiting elements (CLEs) has the potential for use in a dc system. The current commutation ability is vital to the reaction time and the current limiting efficiency of this LMCL. In this paper, the characteristics of a natural current commutation driven by the arc voltage between contacts are first revealed; this method can only be applied in a low-voltage system. To fulfill the demands of a medium-voltage direct current system, an innovative LMCL topology is recommended due to the forced current commutation driven by an auxiliary magnetic induction module. A specially designed structure of magnetic coupling coils with a high coupling coefficient is proposed to improve the current commutation ability. The forced current commutation characteristic is analyzed via simulation and verified experimentally. Furthermore, the arc V–I characteristics of CLEs are deeply discussed to guide the selection of serial quantity of the CLE. Finally, a prototype for the complete LMCL is designed, assembled, and tested in the laboratory. The current limiting coefficient of the LMCL is less than 0.464, the peak value of arc voltage is approximately 6.3 kV, and the current limiting reaction time is 1.53 ms. [ABSTRACT FROM AUTHOR]

A simple buck–boost LED driver suitable for battery operated applications with limited input voltage level is presented in this paper. Soft switching performance is provided for the main switch via a resonant circuit to improve the converter efficiency. The incorporated auxiliary switch also performs under zero voltage switching condition. Both power switches can be driven with a simple gate drive circuit, so, the additional switch does not add any driving complexity. In addition, only one magnetic element is utilized in the proposed LED driver which contributes to circuit simplicity and lower weight and size. Also, all diodes turn off at zero current switching which eliminates the reverse recovery losses and improves efficiency. A laboratory prototype converting 12 V input voltage to 32 V output operating at 26 W output power is implemented and tested to verify the effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In this paper, a novel balancing circuit is proposed, which is well suited to aerospace electronics, as it allows for the use of off-the-shelf radiation tolerant components. The new design was examined analytically with and without a zero-voltage switching topology. Its performance was compared to other popular battery balancing circuits. Further, an equation was derived, which can be used to estimate the time to balance. The proposed balancer circuit was evaluated using forward and several flyback transformer types, and with the use of static and dynamic testing, the design was also evaluated under fault conditions as it provides a short-circuit protection. It was determined experimentally that the proposed design achieves an efficiency of up to 84%. [ABSTRACT FROM AUTHOR]

The challenging demands of pulsed electron beam devices (such as the GESA device) with respect to their pulsed power supply have led to the development of a new semiconductor-based Marx generator. At a maximum output voltage of 120 kV and 600-A pulse current for a duration of up to 100 $\mu \text{S}$ , stepwise arbitrary output waveforms are desired. A fast rise time of the generator is achieved by using fast switching circuitry, low inductance capacitors, and a low inductance stage arrangement. For low jitter triggering of all stages and efficient signal transmission, the generator uses an optical bus system for communication. Due to the inherent dynamic load characteristics of the GESA device, the generator features a fast overcurrent protection scheme. This paper presents selected design aspects of the generator and their validation in a small-scale assembly able of delivering up to 8 kV at 600-A load current. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

This paper presents an optimized switching strategy to reduce the dc-link ripple current for three-level photovoltaic (PV) inverters. The large electrolytic capacitors are commonly used for the dc link of power electronics applications to stabilize the dc-link voltage. The most important factor of designing the dc-link capacitor is the allowable current ripple. The over-ripple current flowing through the capacitor causes a high heat loss, shortened lifespan, low stability, and reliability. The proposed switching scheme selects voltage vectors and reconfigures dwelling order of the vectors to reduce the capacitor ripple current. This switching method is able to extend the lifetime of the dc-link capacitors by simple software programming. In addition, this switching method reduces the common-mode voltage and leakage current that represent high reliability and safety of the system. The effectiveness of the proposed method is verified with simulations and experimental results. [ABSTRACT FROM AUTHOR]

Controlled switching technology operates circuit breakers at the minimum arcing time for short-circuit current interruption. However, there is no report to reveal a relationship between the short-circuit current interrupting capability with the minimum arcing time and the opening velocities of vacuum interrupters. The objective of this paper is to reveal a relationship between the short-circuit current interrupting capability with the minimum arcing time and the opening velocities of vacuum interrupters. A 40.5-kV fast vacuum circuit breaker prototype was built up which was equipped with a commercial 40.5 kV–31.5 kA vacuum interrupter and it was driven by an electromagnetic repulsion mechanism. It provided an average velocities ranging from 2.5 to 5.5 m/s. A total of 50 times of 40-kA short-circuit current interrupting tests were carried out in a synthetic circuit. Test results showed that the minimum arcing time of successful interruption decreased with the increasing of the average opening velocity. The minimum arcing gap was determined as 1.8 mm and it kept as a constant as the average opening velocity increased. The experimental results also showed a relationship between the arc energy density and the arc extinguishing gap, which acted a linear boundary between the successful and failure short-current interruptions. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

As Type-3 wind turbine (WT) has already become a typical type of highly penetrated power sources in modern power systems, characterizing its properties during grid fault is a basic requirement for system analysis. However, many significant factors have not been considered in the existing analytical methods and results, such as various switching of internal control and protection circuits in low voltage ride through (LVRT) solutions. In this paper, performance of Type-3 WT during LVRT is first illustrated and summarized as the sequential switching characteristic in multi time scales, viz., instant control, ac control, dc voltage control, and rotor speed control time scales. Thus, for magnitude drops in stator voltage, a mathematical model is proposed to understand this characteristic and fault current analysis's features. Then, an analytical method, based on the operational inductance, is proposed so that fault current components, with the sequential switching considered, can be depicted with a unified and simple analytical expression. By identifying magnitude of symmetrical current, the transient and steady-state equivalent circuits of Type-3 WT are proposed to estimate momentary current and electrical power approximately. Finally, analytical results are verified by comparisons with real-time simulation results of a detailed 1.5 MW WT model in RT-LAB. [ABSTRACT FROM AUTHOR]

The neutral-point potential fluctuation in single-phase three-level rectifiers leads to coupling between the line current regulation and dc-link capacitor voltage balancing, deteriorating waveform quality of the line current. For addressing this issue, this paper proposes a low-complexity model predictive current control (MPCC) with constant switching frequency, which achieves a decoupling control of the line current and the neutral-point potential under the unbalanced load condition. The switching frequency is fixed by combining the MPCC scheme with predefined switching sequences. The boundary of the durations for voltage vectors in switching sequences is presented to balance the capacitor voltage without worsening the line current quality. The optimal switching sequence and the corresponding optimal durations of voltage vectors in the switching sequence are readily derived without the assessment of the cost function, which dramatically simplifies the complexity of the MPCC scheme. Finally, simulations and experimental results are conducted to verify the effectiveness of the proposed MPCC scheme. [ABSTRACT FROM AUTHOR]

Flyback/forward derived power converters offer operational simplicity, but require active clamping circuits to reduce switch voltage stress and improve the converter efficiency. This paper presents an active clamping circuit technique, which additionally ensures enhancement in the converter voltage gain. This is enabled by the proposed auxiliary circuit, which introduces a charged capacitor in series with the primary source during the energizing interval. Two circuits are designed on this principle, and design and operation of both are presented for discontinuous conduction modes. It is shown that the voltage gain of these circuits increases with increase in the leakage inductance, which is an improvement over existing converters. Also, in one circuit primary (secondary) winding, rms current is similar to (lower than) that in a typical ideal flyback converter, leading to improvement in power density. Operation and analyses of this variant are experimentally verified with a 400-V laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

This paper presents a single event upset (SEU) sensitivity characterization at ultralow bias voltage of three generations of commercial off-the-shelf static random access memories (SRAMs) manufactured in 130-, 90-, and 65-nm CMOS processes. For this purpose, radiation tests with 14.2-MeV neutrons were performed for SRAM power supplies ranging from 0.5 to 3.15 V. The experimental results yielded clear evidences of the SEU sensitivity increase at very low bias voltages. These results have been cross-checked with predictions issued from the modeling tool multiscales single event phenomena predictive platform. Large-scale single event latchups and single event functional interrupts (SEFIs), observed in the 90- and 130-nm SRAMs, respectively, are also presented and discussed. [ABSTRACT FROM AUTHOR]

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series–parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given. [ABSTRACT FROM AUTHOR]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

This paper discusses the voltage error caused by the dead time in voltage-source PWM converters. The theoretical analysis in this paper derives the nonlinear voltage error paying attention to the parasitic output capacitance in each switching device. The analytical result reveals that the turn-off current or the switching current ripple strongly affects the voltage error. In addition, it is clarified that the conventional compensation methods based on linear and three-level approximation are suitable under small and large current ripple conditions, respectively. A simple calculation method of current ripples in three-phase PWM converters is also developed to estimate the turn-off currents. Turn-off transition compensation method which is a new compensation method based on the analysis is developed and compared with three different conventional methods in experiments using a 200-V, 5-kW three-phase grid-connection converter. The proposed method exhibits a good compensation performance having a lower voltage THD than the conventional methods in all over the operating range. [ABSTRACT FROM AUTHOR]

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches. [ABSTRACT FROM AUTHOR]

This paper presents a generalized multilevel direct power control (ML-DPC) scheme for grid-connected multilevel power converters. The proposed method extends the original DPC operating principle by considering only the closest subset of two-level voltage vectors to the present switching state. The implementation of this principle requires the power derivatives for feedback, which can present numerical problems when applied experimentally, mainly due to high measurement noise sensitivity. Therefore, a derivative estimator is proposed based on the converter-grid model in the synchronous reference frame. In addition, a virtual flux observer is developed to achieve synchronization and improve robustness in the presence of grid voltage harmonics. The proposed method is applicable to any multilevel converter topology of any number of levels. In this paper, simulations and experimental results are presented for a seven-level cascaded H-bridge converter. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

The parameters of electrical energy such as voltage amplitude are very important, particularly from the viewpoint of the final consumer and sensitive loads connected to the grid. The dynamic states in the power grid—deep voltage sags and swells—might cause faults and defects in sensitive loads. This paper deals with a three-phase hybrid transformer (HT) without dc energy storage to compensate voltage sags and swells and to protect sensitive loads against the rapid and extensive changes in supply voltage amplitude. The analyzed HT contains two main units: the first one is the conventional electromagnetic transformer, realizing an electromagnetic coupling, and the second one is the buck–boost matrix-reactance chopper, realizing an electrical coupling in the HT unit. In the presented solution, output voltage is transformed in two ways—electromagnetically and electrically. This paper presents an operational description, the theoretical analysis, and the experimental test results from a 2-kVA laboratory model. On the basis of the authors' research, it can be stated that the HT makes it possible to compensate deep voltage sags (deeper than 50% of nominal source voltage) and overvoltages (up to 140% of nominal source voltage) while maintaining good dynamic properties. The main advantages of the proposed solution, in comparison to other conventional solutions, are the ability to control the output voltage in the range of 0.66–3.5 US, good dynamics (transient state during source voltage uS amplitude change is shorter than 10 ms), and galvanic separation between source and load (such as in the case of the conventional electromagnetic transformer). [ABSTRACT FROM PUBLISHER]

Vacuum circuit breaker switching induced transients can cause frequency induced medium voltage transformer dielectric damage, where the two are coupled with short cable. The most common mitigation method is to add a resistor/capacitor snubber at the transformer terminals. While this approach has proved highly effective, there is little discussion of variations on the snubber application. This paper describes the results of switching tests of a vacuum circuit breaker connected to a 1-MVA transformer through medium voltage cable. First, the mechanism was investigated. The tests show the resonance is induced by the broadband frequency content due to the high dv/dt of the circuit breaker current chopping and the chopping rate. Next, snubber performance at various circuit locations was tested. The snubber was most effective at the transformer medium-voltage terminals and at the load side of the circuit breaker. [ABSTRACT FROM AUTHOR]

The paper proposes an optimal control strategy for the interleaved flyback based microinverter to improve its efficiency over the entire operating range. This control scheme is based on the choice of an appropriate operating mode [1-converter discontinuous conduction mode (DCM), 1-converter boundary conduction mode (BCM), 2-converter DCM, and 2-converter BCM] at various instantaneous power magnitudes. The proposed control method reduces the fixed losses associated with the gate driver and the transformer at the low power level. It also reduces the switching losses that may result due to the extremely high-frequency operation of the BCM at the low power level. Additionally, it also reduces the conduction losses through low current peak due to BCM and equal current sharing between the two converters at the high power level. Switching losses, due to the low-frequency operation of the BCM at a high power level, are also reduced. Operating mode selection of the interleaved inverter at a particular power level is based on the information of optimal efficiency. Detailed calculations of peak current references have been carried out for the various operating modes of the interleaved flyback based microinverter. Simulation and experimental results have validated that the proposed control method results in better efficiency compared with the conventional (DCM, hybrid DCM/BCM, hybrid 1-converter/2-converter) control methods with the output current total harmonic distortion remaining within the specified limits. [ABSTRACT FROM AUTHOR]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

A modified scheme for reactive power compensation using static VAr compensators (SVCs) has been proposed in this paper for unbalanced four-wire system. The conventional SVC-based scheme requires both delta ( $\Delta $ $)$ - and star (Y)-connected SVCs for the same purpose. The proposed scheme uses a single-equivalent delta-connected thyristor controlled reactor (TCR) along with a combination of Y- and $\Delta $- connected thyristor switched capacitors for this purpose. The single-equivalent $\Delta $ -TCR in the present scheme is the result of a virtual Y-TCR and the conventional $\Delta $-TCR. This can reduces effective number of switching devices, cost, complexity, and space requirement compared to the conventional SVC-based schemes. Moreover, the proposed scheme can have various advantageous features compared to newly used DSTATCOM. The proposed scheme can also prevent injection of triplen harmonics in to the line, which is injected by Y-TCR in the conventional scheme. An optimized switching function is adopted in the proposed scheme for reduction of additional injected harmonics by TCR. The optimized switching angles are computed offline using gravitational search algorithm and stored in the processor memory for online application. The viability of the proposed scheme is simulated using MATLAB/Simulink and verified by suitable experimental results on a practical system. [ABSTRACT FROM AUTHOR]

This paper presents the concept of three-phase module-integrated converters (MICs) incorporated in grid-tied large-scale photovoltaic (PV) systems. The current-source converter with dc voltage boost capability, namely the single-stage power conversion system, is proposed for the three-phase PV MIC system. A model predictive scheme with low switching frequency is designed to control the proposed topology in such a way that provides a certain amount of active and reactive power in steady-state operation and also provides a proper ratio of reactive power under transient conditions to meet the low-voltage ride through regulations. To predict the future behavior of current control values and switching states, a discrete-time model of the MIC is developed in the synchronous reference frame. It is demonstrated that the injected active and reactive power can be controlled by minimizing the cost function introduced in the predictive switching algorithm. The proposed structure is simulated in MATLAB/SIMULINK software. An experimental verification is provided to justify the performance of the proposed control method through a 300-VA laboratory prototype. The results verify the desired performance of the proposed control scheme for exchanging both active and reactive powers between the PV MIC and the grid within different operating conditions. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper presents a variable switching point predictive current control (VSP $^2$CC) for the quasi-Z-source inverter (qZSI). The proposed VSP $^2$CC aims to remove the output current error on the ac side, as well as the inductor current and capacitor voltage errors of the quasi-Z-source network on the dc side of the converter. Unlike the previously presented direct model predictive control (MPC) strategies for the qZSI, the proposed control scheme can directly apply the switching signals not only at the discrete time instants, but at any time instant within the sampling interval. Consequently, the shoot-through state can be applied for a shorter time than the sampling interval, resulting in lower output and inductor currents ripples. Experimental results based on field programmable gate array are provided to verify the effectiveness of the introduced control method. As it is shown, the proposed method leads to lower inductor current ripples and less output current total harmonic distortion when compared with the conventional direct MPC. [ABSTRACT FROM AUTHOR]

This paper proposes an isolated single-ended primary-inductor converter (SEPIC) dc–dc converter with ripple-free input current and lossless snubber. The proposed converter is based on a conventional isolated SEPIC converter to enable electrical isolation and high voltage gain using a coupled inductor. The input current ripple is significantly reduced by utilizing an auxiliary circuit that also functions as a lossless snubber circuit with an additional diode. Moreover, the maximum switch voltage stress is clamped to a low voltage by the snubber circuit. Therefore, a low voltage rating mosfet that has low $R_{{\rm{DS(on)}}}$ can be utilized as a main switch device. Hence, the total power efficiency is improved. Experimental results from a 100 W prototype, which are presented to verify the theoretic analysis and performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper describes the developed direct current circuit breaker with the grid method (DC CBG). The simplified DC CBG was designed and constructed. It comprises the third electrodes, as the grid of a triode, installed between the main contact electrodes. Moreover, the special-designed transformer (SDT) was designed and constructed to supply a damping high-voltage pulse to the grid electrode for suppressing the arc current. The experiment was conducted to verify the performance of the designed DC CBG. Experimental results show that the amplitude of the arc current was significantly reduced by approximately 94% after the damping high-voltage pulse generated from the SDT was applied to the third electrode. Therefore, the proposed DC CBG has the ability to be developed for practical use in the future. [ABSTRACT FROM PUBLISHER]

In this paper, a class of single-phase Z-source (ZS) ac–ac converters is proposed with high-frequency transformer (HFT) isolation. The proposed HFT isolated (HFTI) ZS ac–ac converters possess all the features of their nonisolated counterparts, such as providing wide range of buck-boost output voltage with reversing or maintaining the phase angle, suppressing the in-rush and harmonic currents, and improved reliability. In addition, the proposed converters incorporate HFT for electrical isolation and safety, and therefore can save an external bulky line frequency transformer, for applications such as dynamic voltage restorers, etc. The proposed HFTI ZS converters are obtained from conventional (nonisolated) ZS ac–ac converters by adding only one extra bidirectional switch, and replacing two inductors with an HFT, thus saving one magnetic core. The switching signals for buck and boost modes are presented with safe-commutation strategy to remove the switch voltage spikes. A quasi-ZS-based HFTI ac–ac is used to discuss the operation principle and circuit analysis of the proposed class of HFTI ZS ac–ac converters. Various ZS-based HFTI proposed ac–ac converters are also presented thereafter. Moreover, a laboratory prototype of the proposed converter is constructed and experiments are conducted to produce output voltage of 110 Vrms / 60 Hz, which verify the operation of the proposed converters. [ABSTRACT FROM AUTHOR]

This paper presents a novel fully integrated step-up dc/dc converter containing circuits to improve electromagnetic emissions. This design utilizes current sources to limit the impulsive current flow into the integrated flying capacitors. This reduces the discontinuous pulse currents normally associated with capacitive converters causing electromagnetic interference (EMI). A variable reference current enables the converter to operate with the lowest possible emissions through the entire operating range and is used to regulate the output voltage. The inclusion of low EMI techniques enables fully integrated power converters to be implemented in systems where noise produced by converters currently restricts or prohibits their use. The proposed 3.2 mW voltage doubler was fabricated in a 0.18 $\mu$m CMOS process. With an input voltage range of 1–1.8 V, the converter produces a 1.6–3.3 V output. Experimental results verify the reduction of emissions to meet IEC 61967-4 Class L using current control with a reduction of noise voltage when compared with the circuit without the proposed techniques. [ABSTRACT FROM AUTHOR]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]