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The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements; therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first-order and second-order all-pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round-off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan-6 and Virtex-6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright © 2017 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

A new design method of an all-digital automatic gain control easy to implement is described and tested. The discretisation of the instantaneous gain provides a recursive form that merges the exponential function with the level detection. The first proposed circuit is well adapted for a software implementation. It comprises a simple control loop and two multipliers. It does neither contain digital filter nor divider and its setting only requires a loop gain parameter. Some tests were conducted on real digital audio signals with a dynamic range of 80 dB and they validate this approach. Under some conditions, the second circuit can even be simpler since it requires only one multiplier. It is well adapted to an field programmable gate array (FPGA) implementation for high speed signal processing. [ABSTRACT FROM AUTHOR]