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With the development of information and communication technology, various types of Internet of Things (IoT) devices have widely been used for convenient services. Many users with their IoT devices request various services to servers. Thus, the amount of users' personal information that servers need to protect has dramatically increased. To quickly and safely protect users' personal information, it is necessary to optimize the speed of the encryption process. Since it is difficult to provide the basic services of the server while encrypting a large amount of data in the existing CPU, several parallel optimization methods using Graphics Processing Units (GPUs) have been considered. In this paper, we propose several optimization techniques using GPU for efficient implementation of lightweight block cipher algorithms on the server-side. As the target algorithm, we select high security and light weight (HIGHT), Lightweight Encryption Algorithm (LEA), and revised CHAM, which are Add-Rotate-Xor (ARX)-based block ciphers, because they are used widely on IoT devices. We utilize the features of the counter (CTR) operation mode to reduce unnecessary memory copying and operations in the GPU environment. Besides, we optimize the memory usage by making full use of GPU's on-chip memory such as registers and shared memory and implement the core function of each target algorithm with inline PTX assembly codes for maximizing the performance. With the application of our optimization methods and handcrafted PTX codes, we achieve excellent encryption throughput of 468, 2593, and 3063 Gbps for HIGHT, LEA, and revised CHAM on RTX 2070 NVIDIA GPU, respectively. In addition, we present optimized implementations of Counter Mode Based Deterministic Random Bit Generator (CTR_DRBG), which is one of the widely used deterministic random bit generators to provide a large amount of random data to the connected IoT devices. We apply several optimization techniques for maximizing the performance of CTR_DRBG, and we achieve 52.2, 24.8, and 34.2 times of performance improvement compared with CTR_DRBG implementation on CPU-side when HIGHT-64/128, LEA-128/128, and CHAM-128/128 are used as underlying block cipher algorithm of CTR_DRBG, respectively. [ABSTRACT FROM AUTHOR]

Among instances when the data and image security in resource constrained environment (smart devices and the like) are to be taken into consideration, lightweight encryption algorithms accede in popularity and are deemed of to be of great merit. In devices as those of the sort mentioned, reducing both power consumption and gate count is always a prime concern. LEA, therefore, triumphs on merit, owing to its low consumption levels of hardware resources, which itself is a result of the adaption of simple modular addition, bitwise rotation and bitwise XOR (ARX) operation instead of the relatively more complex S-box technique. The algorithm in question supports keys of varying sizes three, to be precise: 128, 192 and 256-bit for the intent of providing three levels of image and data security. The hardware implementation of the LEA algorithm for the varying key sizes as mentioned above share significant kinship and hardware resources. This paper puts forward the proposition regarding a high speed low area unified architecture for LEA algorithm for three different sizes of key. The individual hardware implementations of the three key sizes tend to consume more hardware resources than those involved in the proposed unified architecture. The pipelined implementation of the proposed design improves operating frequency to a significant degree, with a little increase in the hardware costs. The design proposed in this paper notably supports three varying tile sizes, i.e. 256 × 256 , 128 × 128 , 64 × 64, of an input image. As resolution of an input image may not necessarily be an integer multiple of the size of tile, smaller tile sizes at the image boundary can also be handled by the same architecture. The design hereby proposed has been implemented on both UMC ASIC 0.09- μ m and XC5VLX330T FPGA platforms and achieved maximum operating frequencies of 740 MHz and 292 MHz respectively. As its increasingly evident on account of the FPGA implementation outcomes, the proposed unified architecture results in vastly improved levels of operating frequency (34%, 33% and 131%) as opposed to the individually available LEA architectures (corresponding to three different key sizes: 128, 192 and 256-bit, respectively). Proposed architecture shows 28%, 35% and 45% increment in the hardware resources with respect to available LEA architectures with single key. The incorporation of the unified key generation technique and pipeline implementation of the algorithm are the main reasons for the more hardware utilization. [ABSTRACT FROM AUTHOR]