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This article analyzes the instantaneous flux trajectory of a permanent-magnet synchronous machine (PMSM) in the six-step operation. Not only the flux dynamics but also the instantaneous voltage vector are included in the analysis. Based on the analysis, a time-optimal voltage vector transition scheme is proposed for the six-step operation of a PMSM. In the proposed scheme, a few steps are added in the transition of the voltage vectors to bring additional degrees of freedom, and they can enhance the dynamic performance conspicuously under the given current constraint. Simulation and experimental results are provided to verify the proposed scheme. For the stepwise torque command, the proposed scheme saves the settling time more than 50% with 60% reduction of the peak current compared to the conventional transition method. [ABSTRACT FROM AUTHOR]

When not all the converters are enabled in a parallel ac/dc power conversion system, some current flows through the disabled converters. This current not only distorts the current waveform of the ac side but also causes extra loss and unintended power flow from the ac to the dc side. In this article, the reason for this current flow is identified, and the total current according to the number of paralleled converters and its operating conditions are analyzed. A new pulsewidth modulation (PWM) method is proposed to minimize the current. And, the zero-sequence voltage and the consequent current flowing through the disabled converters under the proposed PWM method are compared to those under the conventional PWM methods. As a result, it was identified that discontinuous space vector PWM (DPWM) is not a proper PWM method because it causes a large current at some operating conditions. According to both simulation and experimental results, the magnitude of the current flows through disabled converters under the proposed PWM was about 40% less than that under sine PWM and DPWM, and it was about 10% less than that under continuous space vector PWM. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) inverter is the most widely used topology for a medium-voltage drive system due to the high degree of modularity, easier implementation of medium output voltage, and the ability to continuous operation under the cell fault condition. Because each power cell of CHB should have isolated dc source, multiwinding input transformer and three-phase active front end (AFE) are generally used for regenerative applications. The whole system can be simplified by replacing the three-phase AFE with single-phase AFE. However, if the control strategy of normal operation is adopted under the cell fault condition, input power imbalance among three phases inevitably occurs. In that situation, not only faulty cells, but also some unscathed cells should be excluded with giving up the maximum capability of the system, not to deteriorate grid current. This paper proposes a control scheme against the cell fault condition of the single-phase AFE CHB. By applying the proposed control scheme to the system, dc-link voltage of each cell and grid current are well regulated without imbalance even under the cell fault conditions. Finally, it can minimize the number of undamaged cells which should be turned off and maximize the capability of the system under the cell fault condition. Simulation and experimental results are provided to verify the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

In this paper, the characteristics of ripple current of a multimegawatt drive system fed by a pulse-width modulation (PWM) inverter are investigated. Based on the investigation, a novel PWM scheme is devised to reduce the switching loss of the inverter under an identical amount of torque ripple of a motor. The proposed PWM is composed of two parts. The first is minimum torque ripple PWM (MTRPWM), which is optimized in terms of the minimum torque ripple in high modulation index (MI). The second determines the minimum switching frequency while holding the average torque ripple less than the allowable value under various operating conditions. It is termed reduced switching frequency PWM (RSFPWM). Consequently, by simply changing the PWM method from conventional fixed switching frequency continuous PWM to the proposed PWM, MTRPWM and RSFPWM, simulation results show that the switching loss of the inverter driving a 3.5 MW induction motor is reduced to 51.6% while keeping the torque ripple in the allowable boundary, where MI is 1.12. This approach is applied to small-scale experimental sets consisting of an interior permanent magnet synchronous machine (IPMSM) motor-generator set, and an induction machine MG set in an effort to verify the validity and feasibility of the proposed method. Based on these experimental results, the cost indexes of the IPMSM and the induction machine, as defined in this paper, decrease by up to 66% and 77%, respectively, when the proposed method is applied when MI is 1.12 compared with the outcome with the conventional PWM. [ABSTRACT FROM AUTHOR]

In this paper, a resonant damping circuit to suppress the switching ringing of full SiC mosfet is proposed. It reveals that the ringing phenomenon caused by parasitic impedances of switching circuit can be damped out using air core PCB transformer which has a properly designed secondary side circuit. The design method for PCB transformer and the secondary circuit are developed considering the physical dimension applied to the PCB transformer inserted between full SiC mosfet module and snubber capacitor. Experimental results using 1200 V–180 A full SiC mosfet module validate the design method and the performance of the proposed air core PCB circuit. Thanks to the damping circuit, the resonant component due to the switching ringing has been reduced to a half compared to that of system without damping circuit. [ABSTRACT FROM AUTHOR]

Power conversion systems based on double-delta sourced winding (DDSW) had an optimization issue in terms of pulsewidth modulation (PWM). This issue was about inefficient employments of voltage levels during PWM and had to be considered for minimizing voltage stresses and current ripples on DDSW. In this paper, a novel method has been proposed to improve the performance of PWM in DDSW-based systems. The proposed method can be simply implemented as a carrier-based PWM and its principles are neatly summarized with equations. Finally, the effectiveness of the proposed method is demonstrated with experimental results, which were obtained by using a transformer and an induction machine. [ABSTRACT FROM PUBLISHER]

In this paper, it is described how the circulating current flows between inverters that have isolated dc link such as cascaded H-bridge (CHB) topology when they are operating in parallel. In this case, zero sequence circulating current, which normally flows through shared dc link, cannot flow between inverters in parallel. However, circulating current is provoked by asynchronous switching instant of devices, difference of dc-link voltages of parallel inverters, and unbalanced impedance. The circulating current should be suppressed by a sharing inductor that is inserted between inverters. Generally, all of the inverters should synthesize the same output voltage reference for load current control to minimize the size of this sharing reactor. However, this conventional method cannot guarantee diminishing circulating current in the transient state and even in the steady state. In this paper, in order to reduce sharing reactance, after deriving circulating current model from general case of n-parallel operation, circulating current control method is devised based on the model. This proposed algorithm is applied to active front end five-level-CHB inverter system for medium voltage drive. Simulation and experimental results are provided to verify the effectiveness of the proposed control scheme. [ABSTRACT FROM AUTHOR]

In signal injection sensorless drives, the injection voltage cannot be reduced under a certain value. The lower limit of the injection voltage is mainly enforced by the inverter nonlinearity that causes distortion of the injection voltage and degradation of the position estimation performance. After analyzing the inverter nonlinearity during the voltage injection, it is revealed that parasitic capacitances of insulated-gate bipolar transistors have positive effects on inverter output linearity and sensorless control. Based on this analysis, this paper proposes a method to reduce the injection voltage by connecting additional capacitors to the output terminals of the inverter. Simulation and experimental results are provided to verify the effectiveness of the proposed idea. In the experiments, using the capacitor-integrated inverter, it is shown that the injection voltage can be reduced by more than half without degrading the position estimation performance. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

The maximum power point should be continuously tracked in a photovoltaic (PV) inverter. However, the maximum power point could be found at very low dc-link voltages around sunrise or sunset. Then, the overmodulation (OVM) of the inverter has to be considered to keep the power generation even at low dc-link voltages. In this paper, a series of implementation schemes is proposed to keep the current regulation, even if the inverter is under the OVM. These schemes can be helpful to increase the operating time of the PV inverter, which correlates with the daily amount of power generation. After being examined in a small-scale prototype inverter, the proposed method has been tested with a 250-kW PV inverter installed at a proving ground. In a sunset, the operation time of the inverter has been extended by about 12 min, and the generated energy has been increased by 234 Wh, when compared to the normal operation without the proposed methods. [ABSTRACT FROM AUTHOR]

In the square-wave voltage signal injection sensorless drive of the interior permanent-magnet synchronous machine, the injection voltage can be distorted by the inverter nonlinearity effects especially when the injection voltage is low. If that happens, a high-frequency (HF) current signal which contains the rotor position information could be also distorted, which directly leads to an error in the position estimation. This paper analyzes the effects of the inverter nonlinearity on injection voltage, on induced current ripple, and on the position estimation performance in sequence and proposes a voltage injection method to minimize the impact of the inverter nonlinearity by the regulation of the HF current ripple. By simulations and experiments, the performance of the proposed method has been verified. The experimental results show 19.7% reduction of position estimation error under 15% of rated voltage signal injection without increasing the current ripple at a certain operating condition. Moreover, the performance of position estimation is kept uniform regardless of the loading condition. [ABSTRACT FROM AUTHOR]

This paper presents a carrier-based pulsewidth modulation (PWM) method that reduces the common-mode voltage (CMV) of a three-level four-leg converter. Based on an analysis of space vector PWM (SVPWM) and sinusoidal-PWM switching patterns, the fourth-leg pole voltage of a three-phase converter, known as the “f pole voltage,” is manipulated to reduce the CMV. To synthesize the f pole voltage for the suppression of the CMV, positive and negative pole voltage references of the f leg are calculated. In addition, the offset voltage to prevent distortion of the a, b, and c phase voltages regarding the neutral point is deduced. The proposed PWM strategy can be easily implemented in the software of a DSP-based converter control. The three-level four-leg converter with the proposed PWM algorithm results in a remarkable reduction in the peak-to-peak value of the CMV. From the simulation and the experimental results, the peak-to-peak value of the CMV when using the proposed PWM method is 33% compared to that when using the SVPWM method, while the number of CMV transitions during the switching period in the proposed PWM method is only 25% of that when using the SVPWM method. [ABSTRACT FROM PUBLISHER]