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The widespread usage of Long Short-Term Memory (LSTM) accelerators in time-series related applications necessitates using a protection mechanism against faults caused by wear-out and environmental effects. This paper proposes a Concurrent Error Detection (CED) scheme combining low overhead duplication and residue codes to detect faults in multiply and add stages of LSTM accelerators. For the multiply stage, the CED consists of a multiplier for every LSTM multiplier with a temporal selection of data. For the add stage, the CED adders are shared among the LSTM adders, thus spatial selection is performed. The experimental results show that the proposed method yields good detection probability with a lower area and power overhead in comparison with the traditional duplication techniques that indiscriminately duplicate all hardware structures all the time.

The work presented here is on back-annotation of physical properties into components of an embedded system for system-level simulation and facilitating fast design space exploration. Two important properties, power and noise are considered in this thesis. A general ML-based framework is proposed for both power and noise back-annotation. This framework removes the expensive low-level simulations and performs a one-time offline effort for low-level property characterization. The actual data from characterization generates the dataset for training ML-based models. We evaluate several ML techniques on this task like multi-layer perceptron, convolutional neural network, gradient boosting, and LSTM. The trained model will be implemented in a fast SystemC surrogate model that speeds up the simulation time for system design space exploration. In this paper the methodology will be explained for interconnect crosstalk back-annotation. A crosstalk model for a RISC-V like processor interconnects is implemented and evaluated as a case study. The same methodology is used for backannotating and evaluating processor power at system level.

With deep submicron scaling, soft error has become one of the major reliability challenges for electronic systems. This work proposes a Machine Learning-based Checker (MLC) to protect hard-core processors against radiation-induced soft errors. MLC is an independent hardware unit that implements an ML algorithm to detect soft errors in a processor and works in a parallel fashion with that. This work considers XGBoost as a lightweight and high-performance machine learning method. XGBoost is trained based on some programmers’ view features of the processor like control signals. The proposed scheme is applied to a RISC-V-like processor, called SAYAC, as a case study.

This paper presents a design for test (DFT)architecture for fast and scalable testing of array multipliers (MULTs). Regardless of the MULT size, our proposed testable architecture, without major changes in the original architecture, requires only five test vectors. Test pattern generation (TPG) is done by combining C-testability, bijectivity and deterministic TPG methods. Experimental results show 100% fault coverage for single stuck-at faults. The proposed method requires minor testability hardware insertion into the multiplier with extra delay and area overhead of less than 0.5% for a 64-bit multiplier., 6 pages,8 figures