Search

In this brief, a harmonic-controlled substrate-integrated defected ground structure (SIDGS) resonator with tuning capacitor is proposed for the design of tunable filter. Such resonator exhibits a harmonic-controlled characteristic. The fundamental resonant frequency can be properly tuned, while the spurious resonance is controlled at much higher frequency to achieve a wide stopband. To verify the principle, a tunable bandpass filter (BPF) is designed and fabricated based on the resonator. The center frequency can be tuned from 1.75 to 2.7 GHz. Meanwhile, the stopband can extend up to 9.5 GHz with a rejection level of 20 dB for all tuning cases. The BPF also exhibits low insertion loss (i.e., 1.1–1.9 dB) and compact size (i.e., 0.07 ${\lambda _{g}}\,\,{\times }\,\,0.08\,\,{\lambda _{g}}$ , where ${\lambda _{g}}$ is the microstrip guided wavelength at the 1.75 GHz). [ABSTRACT FROM AUTHOR]

This article presents a 22.6–39.2-GHz reflectionless receiver (RX) capable of reducing the in-band intermodulation and high-order mixing products. Such RX consists of an absorptive IF amplifier, a double-balance passive mixer, and a dual-path noise-canceling low noise amplifier (LNA). The absorptive IF amplifier is utilized to suppress the out-of-band signal reflected back to mixer, which can reduce the intermodulation and high-order mixing products caused by the remixing of the out-of-band signals. Meanwhile, the dual-path noise-canceling LNA is used for achieving low noise figure (NF) in a wide frequency range. To verify the aforementioned principle, a reflectionless RX is implemented and fabricated using a conventional 28-nm CMOS technology. The measurement shows the minimum NF of 3.6 dB and the peak input third-order intercept point (IIP3) of −11.7 dBm. Besides, the proposed RX can support multi-Gb/s, 256-quadratic amplitude modulation (QAM)/1024-QAM modulation signals. [ABSTRACT FROM AUTHOR]

In this letter, a packaged bandpass filter (BPF) with a compact size of $1.5 \times 1.5 \times 0.315$ mm3 operating at 28 GHz is proposed. This BPF is implemented based on a multilayers printed circuit board (PCB) fabrication process with ultra-thin substrate. With the packaged configuration, the filter can not only reduce the circuit size and component insertion loss, but also eliminate the effect of electromagnetic (EM) radiation. To verify the mechanisms mentioned above, a packaged millimeter-wave (mm-wave) BPF with three transmission zeros is designed and fabricated. The measured results show that the proposed BPF has the merits of low insertion loss, high selectivity, and compact size. Meanwhile, this BPF can suppress harmonics with a rejection level of more than 24 dB up to 110 GHz. With these merits, the proposed BPF is attractive for 5G mm-wave application. [ABSTRACT FROM AUTHOR]

In this article, a distributed-swing-boosting and harmonic-impedance-expanding multi-core oscillator is proposed to achieve low phase noise and high figure-of-merit (FoM), simultaneously. First, a distributed-coupling multi-core topology is introduced to reduce the chip area with no mode ambiguity. Then, the distributed-swing-boosting and harmonic-impedance-expanding structure is developed to boost the gate swing and square-like waveform of $V_{\text {DS}}$. The common-mode (CM) resonances around the second harmonic and the differential-mode (DM) resonances around the third harmonic are utilized to suppress the flicker noise up-conversion and achieve harmonic shaping. Meanwhile, the dual-resonance response expands the high-impedance frequency ranges around the harmonics, and thus, the effect of harmonic shaping can be obtained over a wide frequency range. Fabricated in a 40-nm CMOS process, the oscillator measured exhibits low phase noise and high FoM simultaneously with a compact chip size. The minimum phase noise is −138.9 dBc/Hz at the 1-MHz offset, corresponding to an FoM of 195.1 dBc/Hz. The 1/ $f^{3}$ phase noise corner is 100–130 kHz over the 26.6% tuning range. [ABSTRACT FROM AUTHOR]

This article presents a quadrature switched/floated capacitor power amplifier (SFCPA) with deep back-off efficiency enhancement. The SFCPA is introduced to decrease the dynamic power consumption at power back-off (PBO), which could improve the system efficiency (SE). The reconfigurable self-coupling canceling transformer (RSCCT) with enhanced tuning range of turn ratio is used to achieve impedance boosting for further improved efficiency at deep PBO. Based on the proposed SFCPA, a watt-level quadrature digital power amplifier (DPA) with IQ cell sharing, hybrid Doherty, and impedance boosting is proposed for deep PBO efficiency enhancement. Implemented in 40-nm CMOS, the proposed DPA with 1.2-/2.4-V supply achieves 30.3-dBm saturated output power ($P_{\mathrm{ out}}$) with 36.6%/32.9%/29.1%/23.7%/18.6%/13.2% SE for 0-/3-/6-/9-/12-/15-dB PBOs at 2.4 GHz. For 60-MHz 256-QAM modulation signal, it delivers 23.32-dBm average output power ($P_{\mathrm{ avg}}$) with an error vector magnitude (EVM) of −31.9 dB and an average drain efficiency (DE) of 30.7%. For 40-MHz 1024-QAM signal, it shows 20.44-dBm $P_{\mathrm{ avg}}$ with an EVM of −35.9 dB and an average DE of 22.6%. [ABSTRACT FROM AUTHOR]

A novel architecture of a digital modulated polar phased-array transmitter with phase modulation (PM) phase-shifting and feed-forward controlled dynamic matching (FFCDM) is presented in this article. Phase-shifting in a PM signal path is utilized in each element, which shares many components including a phase modulator, baseband, and IF components. The characteristics of the proposed architecture are analyzed. With a constant envelope of PM signals, the implicit nonlinearity of the phase shifter in this architecture has low impact on the linearity performance of a phased-array system. Meanwhile, low phase error can be achieved by high-resolution phase interpolation with the digital predistortion (DPD) technique. Efficiency for both saturated and 6-dB back-off power is enhanced by digital power amplifier (DPA) with FFCDM. As a proof of concept, a 3–7 GHz 4-element phased-array transmitter is designed and fabricated in 40-nm CMOS based on the proposed method. The measured root-mean-square (rms) phase error of 0.3°, effective phase shifting resolution of 9-bit, and peak system efficiency of 38.2% are achieved. For 40 MHz 64-QAM modulation signal, it exhibits EVM of 5.38% and 5.37%, $P_{\text {out}}$ of 14.30 and 14.46 dBm, and PAPR of 7.08 and 6.97 at 3.5 and 5.2 GHz, respectively. The measured peak EIRP is 35.6 dBm with a unit antenna gain of 2.98 dBi at 5 GHz. The radiation patterns with 0°, 15°, 30°, and 45° steering are measured based on monopole antennas. Meanwhile, the array achieves < 4.7% and < 5.9% EVM for 64-QAM signals with bandwidths of 20 and 40 MHz, respectively. [ABSTRACT FROM AUTHOR]

In this article, a 22.9–38.2-GHz dual-path noise-canceling low noise amplifier (LNA) is proposed, which can achieve a low noise figure (NF) by reducing the noise of both paths. Such LNA consists of one common gate (CG) amplifier with one three-stage transformer, one resistive feedback common-source (CS) amplifier, and two amplitude-adjusting amplifiers. The three-stage transformer is used in the CG amplifier to provide gain-boosting, noise-reducing, and wideband inter-stage matching operation, simultaneously. Meanwhile, amplitude-adjusting amplifiers with reconfigurable phase-tuning lines are utilized in both paths to optimize the noise-canceling performance. To verify the aforementioned principle, a dual-path noise-canceling LNA is implemented and fabricated using a conventional 28-nm CMOS technology. The proposed LNA consumed 18.9 mW under a 0.9-V supply. The measured NF is 2.65–4.62 dB within the operating frequency range of 22.9–38.2 GHz, while the peak gain is 14.5 dB. The in-band input 1-dB compression point (IP1 dB) and input third-order intercept point (IIP3) are −13.2 to −6.6 and −3.6 to 3.2 dBm, respectively. [ABSTRACT FROM AUTHOR]