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Motivated by the transition to renewable energies in the context of ongoing climate change, offshore wind energy is of rising importance for the energy provision on national and international level. This trend, though, puts pressure on the safety and security community to provide appropriate analyses and solutions in regard to safety and security threats. Based on this motivation, this work investigates the internal disturbances in Offshore Wind Farms (OWF) provoked by cyber-attacks and severe electrical faults that might lead to high impact events. Therefore, the influences of these disturbances are quantified using a simulation model that represents electrical and mechanical aspects as well as the protection and control system. Furthermore, the dependence of the system response on to the disturbance characteristics is determined and the critical values of the disturbance characteristics leading to the OWF service interruption or even physical damage are identified. The results indicate in quantitative manner processes in the electrical and mechanical systems during parameter manipulations due to cyber-attacks and severe electrical faults. This, together with the quantitative signatures of the disturbances, enable future improvements of the security and stability of OWF systems. • Quantitative impact study of manipulations due to cyber-attacks on Offshore Wind Farms (OWFs). • Quantitative impact study of severe electrical faults on service provision of OWFs. • Application of Disturbance Impact Index for vulnerability analysis of OWFs. [ABSTRACT FROM AUTHOR]

Coarse grain reconfigurable architectures (CGRAs) are an emerging hybrid computational architecture that has the parallel customization benefits of low-level logic devices, such as FPGAs and ASICs, while the relative coarseness of these architectures makes CGRAs easier to design for, which is more similar to the traditional processor. In the process of mapping designs to CGRAs, flexible, fast, and adaptive placement and routing (P&R) is fundamental in order to implement efficient run-time reconfigurable frameworks. It is well-known that P&R is an NP-complete problem, and thus, solutions rely on heuristics to achieve quality results with acceptable execution times. CGRA P&R has different constraints compared to traditional VLSI P&R, e.g., path latency balancing and modulo scheduling of loops. In this work, we propose a graph-based P&R approach that uses graph traversals to map designs to CGRAs. Additionally, we parallelize our approach with a graph-based greedy heuristic that executes on a GPU. We compare our proposed P&R approach with the CGRA-ME framework, which implements simulated annealing and integer linear programming placement algorithms. Our results show that this new approach can generate optimal mappings and improve the execution run-time up to several orders of magnitude. Furthermore, considering spatial mapping at the millisecond scale, our GPU approach is one order of magnitude faster compared to the state-of-the-art tool VPR. [ABSTRACT FROM AUTHOR]