6 results on '"Navabi, Zainalabedin"'
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2. A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies
3. Compiling an RT level hardware description language into layout of NMOS cells
4. Generating gate level two phase dynamic MOS logic from AHPL
5. Compiling gate RC models into a top level simulation model for rough timing analysis of VLSI circuits
6. Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models
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