8 results on '"Qian, Huizhen Jenny"'
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2. Low NF and High P1dB Wideband Quasi-Circulator With Unequal Power Split and Reconfigurable Inter-Stage Matching.
- Author
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Chen, Wen, Deng, Zhixian, Shu, Yiyang, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
INSERTION loss (Telecommunication) ,TRANSMITTERS (Communication) ,CAPACITORS - Abstract
In this article, a wideband quasi-circulator (QC) with the low noise figure (NF) and high 1-dB compression point (P
1dB ) is proposed. The slotline-based 180° hybrid is introduced to achieve the wideband high transmitter-receiver (TX-RX) isolation. Meanwhile, the bidirectional in-phase stage and the nonreciprocal out-of-phase stage are utilized to obtain specific power-split ratios for the low insertion loss and high antenna-transmitter (ANT-TX) isolation. By using the unequal power split, the proposed QC is without the fundamental 3-dB loss seen in reciprocal ANT interfaces. Besides, to further enhance the TX-RX isolation within a wideband, a reconfigurable inter-stage matching network based on a varactor-tuned capacitor is implemented. To verify the mechanisms mentioned above, a reconfigurable wideband QC operating at 1.75–2.9 GHz is implemented and fabricated. The total power consumption is 224 mW. The measurement exhibits in-band TX-RX isolation of 27–58 dB. The TX-ANT and ANT-RX insertion losses are 4.3–5.0 dB and 1.0–1.9 dB, respectively. The QC also achieves the minimum in-band ANT-RX NF of 3.4 dB. Meanwhile, the measured TX-ANT and ANT-RX IIP3s are 39.4 and 32.5 dBm, respectively. The TX input P1dB is greater than 28.78 dBm, while the RX input P1dB is 23 dBm. The TX-induced ANT-RX P1dB is measured to be 28 dBm. [ABSTRACT FROM AUTHOR]- Published
- 2021
- Full Text
- View/download PDF
3. Substrate-Integrated Defected Ground Structure for Single- and Dual-Band Bandpass Filters With Wide Stopband and Low Radiation Loss.
- Author
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Tang, Deshan, Han, Changxuan, Deng, Zhixian, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
BANDPASS filters ,TRANSMISSION zeros ,RADIATION - Abstract
In this article, two types of substrate-integrated defected ground structure (SIDGS) resonant cells with wide upper stopband and low radiation loss are presented for filter implementation. Such SIDGS resonant cells are composed of two dissimilar DGSs surrounded by the bottom ground and metal-vias, which cannot only introduce wide stopband with low radiation loss but also be flexible for integration. Based on the aforementioned SIDGS resonant cells, single- and dual-band bandpass filters (BPFs) are designed and fabricated. The single-band BPF centered at 2.40 GHz exhibits an ultrawide upper stopband up to 19.7 GHz with a rejection level of 31 dB, whereas the measured stopband total loss (i.e., including radiation, metal, and substrate loss) remains about 30% up to 19.3 GHz. The dual-band BPF operated at 2.10 and 3.78 GHz exhibits an ultrawide upper stopband up to 17.8 GHz with a rejection level of 23 dB, whereas the measured stopband total loss is less than 16% up to 11.4 GHz. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
4. High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology.
- Author
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Zhou, Jie, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
- *
PHASE shifters , *DIGITAL-to-analog converters , *VOLTAGE references , *VOLTAGE control - Abstract
In this paper, a wideband vector-sum phase shifter with phase linearity enhancement technology is proposed to minimize phase error. The digital phase shifter synthesizes the output phases by modulating and summing four quadrature signals. A common-source stage with transformer-based matching network and a quadrature-all-pass filter (QAF) are utilized for the quadrature signals generation within a wideband. Besides, to decrease the influence of parasitics on amplitude and phase error, a resistor-based compensation technology is employed in the QAF implementation. Then, to obtain the 360° range high resolution phase shifts, the quadrature signals are modulated by four Gilbert-type variable gain amplifiers (VGAs) with digital-controlled current-digital to analog converters (current-DACs). To further minimize phase error, an on-chip phase linearity enhancement loop is utilized. The drain voltages of current-DACs are detected and compared to the presupposed reference voltages generated by the loop. Besides, the compared results are fed back to control the current-DACs to achieve phase linearity enhancement. To verify the mentioned mechanism, a 7-bit digital phase shifter operating at 22–44 GHz with on-chip phase linearity enhancement technology is implemented and fabricated in a 28-nm CMOS technology. Based on the phase linearity enhancement technology, the phase shifter exhibits a RMS amplitude error of 0.36–0.59 dB and RMS phase error of 0.92° −1.02° without off-chip digital pre-distortion (DPD) technology. The total DC power consumption including the phase linearity enhancement loops is 35 mW under a 0.9V supply voltage. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
5. A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator.
- Author
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Shu, Yiyang, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
- *
PHASE noise , *QUADRATURE domains , *VOLTAGE , *PHASE-locked loops , *FREQUENCY synthesizers - Abstract
A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are −188.2 dBc/Hz and −200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from −104.1 to −108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is −236.2 dB. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
6. A 169.6-GHz Low Phase Noise and Wideband Hybrid Mode-Switching Push–Push Oscillator.
- Author
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Shu, Yiyang, Qian, Huizhen Jenny, and Luo, Xun
- Subjects
- *
PHASE noise , *RESONATORS , *NONLINEAR oscillators , *ELECTRIC inductance - Abstract
A wideband hybrid mode-switching push–push oscillator with low phase noise is presented in this paper. To achieve the wide tuning range, the inductive and capacitive hybrid mode-switching technique is proposed for the first time. It introduces more freedom of design parameters (i.e., inductance and capacitance) in the resonant tank. Under certain tuning range requirement, the hybrid mode-switching oscillator achieves higher input impedance of the resonator compared to the conventional mode-switching oscillators. Meanwhile, a transformer-coupled inductor ring with symmetrical layout configuration is proposed to realize the switch-less hybrid mode switching, which further improves the circuit performance at sub-THz. Therefore, a good phase noise performance can be obtained within a wide tuning range, which leads to a relaxed tradeoff between the phase noise and tuning range. To verify the aforementioned mechanism operating at sub-THz band, a hybrid mode-switching oscillator based on the dual-mode push–push topology is proposed and fabricated in a conventional 28-nm CMOS technology. The measured results show a 21.7% tuning range with the center frequency of 169.6 GHz and a state-of-the-art FoMT of −180.6 dBc/Hz. The core circuit only occupies 0.039 mm2, while drawing 95 mW with a 0.9-V supply. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
7. Adaptive Synthesis for Resonator-Coupled Filters Based on Particle Swarm Optimization.
- Author
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Luo, Xun, Yang, Bingzheng, and Qian, Huizhen Jenny
- Subjects
PARTICLE swarm optimization ,BANDPASS filters ,MATHEMATICAL optimization ,SIMULATION methods & models ,BANDWIDTHS ,ALGORITHMS - Abstract
In this paper, an adaptive synthesis using the particle swarm optimization (PSO) for implementations of resonator-coupled filters is proposed. The coupling matrix of in-band filtering response is achieved and optimized by the PSO-based synthesis. Meanwhile, the stopband coupling matrix of the filter is predicted based on the combination of extra resonant nodes representing stopband spurious and parasitic effect of input/output ports. In addition, an enhanced accurate prediction of filter performance is calculated by the proposed approach, considering the practical fabrication tolerance on filter design. To verify principles mentioned earlier, various resonator-coupled filters are implemented. The calculation, EM-simulation, and measurement of filters show good agreements in both passband and stopband. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
8. Wideband Digital Power Amplifiers With Efficiency Improvement Using 40-nm LP CMOS Technology.
- Author
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Qian, Huizhen Jenny, Liang, Jian Orion, and Luo, Xun
- Subjects
- *
POWER amplifiers , *COMPLEMENTARY metal oxide semiconductors , *ULTRA-wideband devices , *BANDWIDTH research , *ELECTRIC impedance - Abstract
In this paper, two fully integrated digital power amplifiers (DPAs) intended for polar transmitters are proposed using a 40-nm CMOS technology, which achieve ultra wideband and high efficiency simultaneously. Firstly, the wideband Class-E power amplifier with nonideal characteristics is analyzed. Secondly, the design procedure of converting the nonideal Class-E model to a compact matching network is introduced for the on-chip implementation. Thirdly, the stacked-stepped-impedance transformer is utilized for the wideband output-matching network to improve the DPA power efficiency while tracking optimum load impedance. Finally, to enhance the saturated and back-off efficiency within a wideband, a novel feed-forward DPA architecture for a digital polar transmitter with multi-mode dynamic-matching (DM) network is firstly introduced and demonstrated. To verify the mechanism mentioned above, two DPAs are implemented and fabricated, which are the only reported wideband DPAs operating above 3 GHz with record fractional bandwidths, i.e., 92% and 100.8%, respectively. The proposed DPAs (i.e., DPA-I and DPA-II) exhibit peak output power of 22.2 and 22.3 dBm and peak drain efficiency of 46.2% and 47.4%, respectively, with a 1.2-V supply. In DM modes, the saturated and 6-dB back-off drain efficiency of DPA-II achieve maximum improvements of 7.5% and 5.7%, respectively. The core chip-sizes of the proposed DPAs (i.e., DPA-I and DPA-II) are 0.22 mm^2 and 0.24 mm^2, respectively. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
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