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In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

The drain induced dynamic threshold voltage (${V}_{\textrm {th}}$) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance (${C}_{\textrm {GD}}$) is charged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$. The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$) $- {Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]