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In recent years, electrophoretic display (EPD) attracts great attention for its ultra‐low power consumption, which is suitable for self‐powered applications. In this case, an energy storage system, simple as the capacitor, is essential for the self‐powered driving of EPDs. However, significance on the capacitor‐based driving of EPDs was underestimated in spite of its great practical value. This paper investigated the capacitor‐based driving of EPD for better performances of self‐powered EPDs. Based on this novel scheme, sports shoes with self‐powered EPD patterns were demonstrated as the future wearable applications. [ABSTRACT FROM AUTHOR]

Vertical, organic, light‐emitting transistors (VOLETs) combine three of the four essential components of an active matrix lightemitting diode (AMOLED) pixel ‐ the drive transistor, the storage capacitor, and the OLED stack ‐ into a single, highly‐stable, selfemissive structure. VOLETs can be manufactured on amorphous silicon (a‐Si) thin‐film transistor (TFT) backplanes to enable lowcost AMOLED displays with improved brightness and lifetime characteristics. We report on the current status of VOLET development and prospective impact on the active‐matrix display industry. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to better design the resonant tank parameters for LLC resonant converter. And, it is found that under heavy load, the voltage gain is affected by junction capacitors of the primary side switching and the parasitic parameters of the secondary side diodes converted to the primary side, which will cause the voltage gain decreased when the switching frequency decreased. Design/methodology/approach: This paper proposes an optimization parameters design method to solve this problem, which was based on impedance model considering the parasitic parameters of switching devices and diodes. Findings: The effectiveness of the proposed method is verified by impedance Bode plots and experimental results. Originality/value: From the perspective of impedance modeling, this paper finds the reasons for the insufficient voltage regulation capability of LLC resonant converters under heavy load and finds solutions through analysis. [ABSTRACT FROM AUTHOR]

The metalized film capacitors (MFC) in converter valves are subjected to high-frequency currents under the action of power electronic switching, which will cause large differences in currents among capacitor elements inside MFC and seriously affect the stability of MFC. In this paper, experiments were conducted to measure the current waveforms among 90 elements under impulse, short-circuit discharge and sine waves at different frequencies. The equivalent circuit topology was simplified by using decoupling and controlled source equivalence, and parameters were extracted by electromagnetic calculations combined with experiments. Finally, an equivalent circuit model was established and the current distribution among elements was calculated. Influenced by the reactance of the parasitic inductor and the capacitor element, the frequency range can be divided into 3 regions based on the current distribution characteristics: in the high frequency range (>100 kHz), the current is mainly concentrated on several capacitor elements near the connection terminals. In the middle frequency range (about 10 kHz–100 kHz), the current oscillates between elements and the inductor, resulting in a wavy distribution of current amplitude, strongly influenced by frequency. In the low frequency range (<10 kHz), the current distribution varies very little among 90 elements. These results can support the study of performance evolution, fault analysis and design optimization in MFC. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase, transformer-less, seven-level inverter that utilizes eight switches, three capacitors, and two diodes to produce seven voltage levels with triple boosting ability. The availability of the common-ground point eliminates the leakage current in PV applications. The proposed Transformer-Less Triple-Boosting Seven-Level Inverter (TLTB7LI) has the ability to feed different types of loads from non-unity to unity power factors. The voltage balancing of capacitors takes place naturally without the need for auxiliary circuits and complicated control strategies. This paper investigates the appropriateness of the proposed TLTB7LI for grid-connected application. The Peak Current Controller (PCC) is employed to generate the switching pulses and regulate the active/reactive power transfer between the converter and the output, which guarantees the high quality of injected current to the output. Moreover, the operational principles, its control technique, as well as the design procedure of the key components of the proposed inverter have been presented. The superiority of the proposed inverter over existing counterparts has been verified through comparative analysis. The simulation and experimental analysis validated the proper operation of the proposed TLTB7LI. [ABSTRACT FROM AUTHOR]

A grid-forming wind generation system exhibits exceptional grid frequency support abilities. The DC capacitor of the grid-forming wind generation system, which is characterized by rapid response and high sensitivity to minor disturbances, can provide short-term inertia support for the power system. This paper proposes the capacitor virtual inertia control for the grid-forming wind generation system, coupling the DC capacitor voltage with the power system frequency, which enables the DC capacitor to participate in the system frequency response process and reduces the rate of change of the system frequency during the disturbance. To analyze the inertia of the wind power generation system, this paper establishes an equivalent Philips-Heffron model for the grid-forming wind generation system and uses the equivalent inertia constant to quantify the inertia of the wind power generation system. The effectiveness of the proposed control strategy and the reasonableness of the inertia assessment method are verified through simulations in the single-turbine system and the IEEE four-machine two-area system. [ABSTRACT FROM AUTHOR]

Power converters enhance the DC-AC power supply by using multi-level inverters based on switched capacitor technology. The voltage stress on the switches in switched capacitor-based multi-level inverters decreases as the number of switches rises, and vice versa when the number of switches falls. This paper suggests a quadruple boost nine-level inverter based on a switched capacitor with a single voltage source to address this issue. Only nine switches are used in the suggested architecture to implement the inverter with two diodes and two capacitors. Since the diodes and capacitors are linked to the low voltage input side, the total voltage stress of the inverter is kept low even at the elevated for quadruple boost output voltage. The theoretical study, computations, and design parameters of the nine-level inverter are presented in this paper. The switching specifics of the seven-level boost extension topology are also reported in this work. Simulations and laboratory tests on a 120 W inverter prototype have confirmed the viability of the suggested topology. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a 1-bit full adder is proposed based on dynamic logic methodology, which utilises pass transistors. The clocking operation falls into two phases. The clocking operation consists of a pre-discharged cycle, during which pseudo capacitors are reset to zero when the clock signal is high, and an evaluation cycle, during which the circuit outputs the adder function when the clock signal is low. The circuit uses a combination of 12 pass-transistors to better implement the full adder logic function with the maximum of a NMOS threshold voltage drop. Moreover, the circuit has no direct connection to the power-supply node and so this can possibly save the power dissipation. Our new adder outperforms other 1-bit full adder structures in terms of power-delay factor, according to simulation results. [ABSTRACT FROM AUTHOR]

This research paper introduces an innovative modulation technique for controlling a 3-level flying capacitor multilevel inverter (FCMLI), aiming to streamline the modulation process in contrast to conventional methods. The proposed simplified modulation technique paves the way for more straightforward and efficient control of multilevel inverters, enabling their widespread adoption and integration into modern power electronic systems. Through the amalgamation of sinusoidal pulse width modulation (SPWM) with a high-frequency square wave pulse, this controlling technique attains energy equilibrium across the coupling capacitor. The modulation scheme incorporates a simplified switching pattern and a decreased count of voltage references, thereby simplifying the control algorithm. [ABSTRACT FROM AUTHOR]

In today's healthcare landscape, MRI (magnetic resonance imaging) plays a pivotal role in early diagnosis and treatment decisions. However, the quest for higher frequencies to achieve micron‐level resolutions poses technological challenges. This paper focuses on coils and capacitors, with special attention to air gap considerations for movable electrodes. The paper delves into the development of adjustable capacitors using high‐fired NP0 ceramic, tailored for 128‐MHz MRI systems. These capacitors boast impressive specs: a 3‐kV breakdown voltage (VBreakdown), a 3‐pF minimum capacitance (Cmin), a 30‐pF maximum capacitance (CMax), and a 1.5‐pF stepwise capacitance variation (Cvariation step). Notably, they enhance breakdown voltage while preserving frequency stability with MgTiCa ceramic between the fixed and mobile electrode, critical for adaptive blocks. Leveraging geometrical parameters analyzed through the ANSYS simulator, the authors meticulously designed an optimized 25–40 pF capacitor with a 15‐mm height and 1600 mm2 surface area. Post‐fabrication and sintering, extensive testing using a vector network analyzer across 10 MHz to 100 MHz validated performance against simulated expectations. [ABSTRACT FROM AUTHOR]

In photovoltaic grid-connected systems, the interaction between grid-connected inverters and the grid may cause harmonic oscillation, which severely affects the normal operation of the system. To improve the quality of the output electrical energy, photovoltaic grid-connected systems often use LCL filters as output filters to filter out high-frequency harmonics. Taking the three-phase LCL-type photovoltaic grid-connected inverter system as an example, this paper addresses the issue of harmonic resonance. Firstly, based on the harmonic linearization method and considering the impact of the coupling compensation term on the grid-side voltage, a modular positive and negative sequence impedance modeling method is proposed, which simplifies the secondary modeling process of the converter under feedback control. Then, the stability analysis is conducted using the Nyquist criterion, revealing the mechanism of high-frequency resonance in photovoltaic grid-connected systems. Furthermore, this paper delves into the impact of changes in system parameters on impedance characteristics and system stability. The results indicate that the proportional coefficient of the internal loop current controller has a significant influence on system impedance characteristics. Additionally, this paper proposes an active damping design method that combines lead correction and capacitor current feedback to impedance-reconstruct the easily oscillating frequency band. Finally, the effectiveness of this method is verified in the simulation platform. Simulation results confirm the effectiveness of this method in suppressing harmonic resonance while maintaining rapid dynamic response. [ABSTRACT FROM AUTHOR]

This paper presents an investigation into the performance of radial distribution systems (DS) with the installation of series capacitors in feeder sections. While the use of shunt capacitors to enhance voltage profile in DS has been acknowledged, the benefits of series capacitors have only been explored to a limited extent. Load flow analysis, while commonly used for offline evaluation of DS, can at times yield inconclusive results due to convergence issues. To mitigate this, an alternative approach is proposed using Artificial Neural Networks (ANN) to directly determine system performance. The viability of the proposed technique is evaluated for IEEE 12 and IEEE 33 bus DS's having series capacitor in feeder section for voltage improvement and line loss minimization. Therefore, this paper serves to contributes to the two main novelties namely, (1) Development of efficient ANN model to directly determine the maximum voltage regulation and line losses and (2) improvement of voltage and line losses reduction through series capacitor installation in feeder section of the DS. The results show that the utilization of an ANN model enhances accuracy and speeds up predictions, while the installation of series capacitors in feeder sections improves voltage regulation and reduces line losses. [ABSTRACT FROM AUTHOR]

Extensive research on the multi-bridge extension of cascaded rectifier stages is deemed important to meet the requirements of high-voltage and high-power applications. Two control structures for capacitor voltage balancing in cascaded rectifier stages are analyzed in this paper. On this basis, the balance strategy for the multi-bridge extension of single-phase cascaded rectifiers is explored. The balance method of ultra-fast balance modulation trajectories is introduced into single-phase multi-bridge cascaded rectification, and the optimal control strategy is selected through simulation verification and comparative analysis. During the actual experiments, some disturbance factors were introduced into the system, causing an instantaneous unbalanced state. However, through the control strategy proposed in this paper, the system can quickly regain balance. Through simulation validation and analysis of the experimental results, the reliability and innovation of this control strategy have been demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents the performance analysis of a five-level T-type multilevel inverter (MLI) based six-phase induction motor drive (SPIMD) for high-power industrial applications. In the adopted T-type MLI, the sensorless self-capacitor voltage balancing control is designed, which controls the voltage across the capacitor at half the magnitude of the direct current (DC) source value, creating a symmetrical five-level output voltage waveform. Moreover, self-capacitor voltage balancing control reduces complexity and improves system performance. The SPIMD with distributed neutral is taken as the load, and the whole system is simulated using MATLAB/Simulink software. The system's performance is determined by considering the power loss and efficiency. This paper also presents a comparative performance analysis of the adopted T-type, cascaded h-bridge (CHB) and Flying Capacitor (FC) MLI-based SPIMD. Finally, a prototype is developed as a proof of concept and tested experimentally to validate the analytical development of the adopted system. [ABSTRACT FROM AUTHOR]

The increasing demand of electrical energy has attracted researchers, engineers and designer to focus and investigate further for clean energy sources. The conversion of renewable energy to electric involve use of generators. The concept of induction generator has been addressed by many researchers till date. Nowadays, demand is to further extend the application of induction machine as motor and induction generator in electric vehicles as well. During the regenerative breaking of electric vehicles, the induction machine can serve as induction generator provided appropriate capacity excitation is given. For an electric vehicle the actual speed virus depending upon road conditions, traffic and the driving skills. Hence the induction machine in such an application shall be capable of working as a generator for variable speed operations. The induction generator offers many advantages such as robust and maintenance free construction (squirrel cage), inherent overload protection, configurability etc. This paper discusses the effect of excitation capacitor on the output voltage of self-excited induction generator at variable speed and variable loading conditions. The experimental results of a case study are presented. [ABSTRACT FROM AUTHOR]

Nano gap capacitors have recently received significant interest as a key component in a wide range of implementations including photonics, Nanoelectronics, and sensing applications. Many exploratory research projects are being conducted to investigate the electrical characteristics of these nano capacitors. One essential issue that this paper addresses is the need for highly sensitive nano gap capacitors which can be adopted for ultra-low power sensing implementations. In this paper, gold is utilized as the electrode material owing to its superb chemical stability, electrical conductivity, and biocompatibility. The fabrication process is started by designing the mask namely nano gap pad electrodes using AutoCAD software. Subsequently, the designs are finally transferred and fabricated onto a chrome glass surface. In this work, after a combination of conventional photolithography and size reduction approach used to fabricate the device, conventional photolithography is applied to transfer the nano gap pattern onto the gold surface. In order to achieve the desired dimension of the nano gap, a size reduction technique is employed. Describe the most important thing in 2-3 sentences only). Visual inspection using a High Power Microscope (HPM), 3D nano profiler, X-Ray diffractions (XRD), and Field Emission Scanning Electron Microscope (FESEM) have been employed to observe and validate the fabricated structures. Results show that a 2.5 nano Ampere is measured as the applied voltage increases to 10 mV. This firmly demonstrates the ultra-low power consumption, several Pico watts, of these nano gap capacitors. Further, our findings show that the fabricated 4nm gap structure can achieve an approximately 300 nano farad capacitor at low frequencies, which is advantageous for adoption in highly sensitive biosensors. [ABSTRACT FROM AUTHOR]

This paper discusses in detail a new 17-level inverter that employs a switched-capacitor (SC)-based configuration. The proposed SC-based inverters require just a single DC power supply, three capacitors, four diodes and 13 switches. The peak inverse voltage of the proposed 17-level SC-based inverter half-bridge is cut in half when compared to the prior arrangement, which was published not long ago. The blocking voltage is reduced by an order of magnitude as well. Many of the features of the proposed SC-based inverter, such as a high boosting gain factor (G) of eight times, self-balanced capacitor voltage and decreased voltage ripples in capacitors, have been carried over to other SC-based MLIs. The circuit description, working theory, PWM modulation techniques and capacitor voltage ripples are all examined. Finally, the results of the experiments show without a doubt that the proposed SC-based inverter can be made. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology for Z-source inverters (ZSI). The new Z-Source network is based on the coupled-inductors and active switched boost. Features of the topology include high voltage boost ability, single magnetic-core, low voltage stress on the active switch, and capacitors. The principles of operation, analysis, voltage and current equations of each component, and the converter voltage gain in the steady-state are presented. A comparison with other topologies has also been performed to determine the advantages and disadvantages of the proposed ZSI. Finally, experimental results of the laboratory prototype are presented to confirm the performance of the proposed topology. [ABSTRACT FROM AUTHOR]

Grid-forming (GFM) wind storage systems (WSSs) possess the capability of actively building frequency and phase, enabling faster frequency response. The frequency regulation power of GFM WSSs is provided by both the rotor of wind turbine and the battery storage (BS) in parallel with DC capacitor. However, with existing control strategies, the energy storage immediately responds to both small and large grid disturbances. The frequent responses significantly decrease the lifespan of energy storage. To address this issue, a cooperative strategy between rotor and energy storage is necessary. This paper proposes an advanced strategy of GFM WSSs for cooperative DC power support. The cooperative principle is that for small disturbances, the BS is disabled and total frequency regulation power is provided by the rotor, while for large disturbances, the BS is enabled to cooperatively provide power support with the rotor. The proposed cooperative strategy can decrease the charging and discharging times of BS with a small range of rotor speed fluctuation, and then the service life of BS can be significantly extended. Simulation results validate the effectiveness and superiority of the proposed strategy. [ABSTRACT FROM AUTHOR]

A three‐level neutral point clamped (3L‐NPC) voltage source inverter (VSI) topology can be advantageous in electric vehicles with a high DC‐link voltage and a high switching frequency. A bulky DC‐link capacitor is not an option; thus, the DC‐link capacitor's sizing considering the traction system characteristics is an important design step. This paper investigates how the DC‐link capacitor size of a 3L‐NPC VSI gets affected by the combination of the interdependent characteristics of an electric drive, such as its power factor, modulation index, current, and fundamental frequency, with the effects of the modulation methods. Five pulse width modulation (PWM) methods, of which three of them have an active neutral point potential control, are compared in terms of their neutral point potential (NPP) oscillations. Then, the size of the DC‐link capacitor is determined for each PWM method so that the NPP ripple is kept under desired limits at all operating conditions. It is shown that both the modulation technique and the electric machine characteristics influence the capacitor size. For example, electric machine design modifications can introduce more than a 30% reduction in capacitor size. Finally, DC‐link and NPP oscillations with different PWM methods are experimentally validated in a scaled‐down 3L‐NPC inverter. [ABSTRACT FROM AUTHOR]

The present paper is concerned with a magnetorheological (MR)-damper-based vibration-reduction system with energy harvesting capability considering sprung mass changes. The system represents a mechanical harmonic oscillator with electrical coupling, set in motion by kinematic excitation. The authors examine the system performance in the case when the MR damper control coil (damper control coil) is powered directly by the alternating current resulting from the voltage generated in an electromagnetic harvester in the assumed frequency range of sine excitation. Such a system is able to attenuate vibration in the near-resonance frequency range when the current in the damper control coil increases; however, its drawback is vibration amplification at higher frequencies. To eliminate this negative feature, it is proposed to connect shunt capacitors in parallel with the damper control coil. Then, the system can be tested experimentally in terms of current in the damper control coil, sprung mass, and the capacity of shunt capacitors in order to evaluate system performance according to the assumed performance index. The obtained results demonstrate significant improvement in system performance at higher frequencies of excitation. [ABSTRACT FROM AUTHOR]

Summary: A setting‐zero analysis method is presented to facilitate the prediction of zeros in multistage amplifiers. The main objective of this method is to simplify the analysis process of such amplifiers while improving the overall performance, and the feasibility is confirmed by various examples presented in this paper. By proposing a single‐capacitor cascode Miller compensation three‐stage amplifier using setting‐zero analysis, this paper has theoretically verified that the addition of a grounding second‐stage compensation capacitor is unnecessary. Measurement results show that this amplifier consumes a current of 38 μA at a 1.2 V supply voltage, with a 103 dB open‐loop gain. When driving a 1 nF load capacitor, this design achieves 1.88 MHz gain bandwidth and 73° phase margin, with a 3.33 V/μs average slew rate and an average 1% settling time of 0.40 μs under the unity‐gain configuration. [ABSTRACT FROM AUTHOR]

In order to cope with the failure of existing fault analysis schemes for AC/DC distribution networks with a high proportion of distributed generations, this paper proposes a fault characteristic analysis method for AC/DC distribution networks that considers the influence of distributed generation control strategies. Firstly, a transient model for the AC/DC distribution network connected to distributed generations is built. Then, the fault characteristics of the AC/DC distribution network in different stages, such as the capacitor discharge stage, inductive renewal stage, and steady state stage, is analyzed. Finally, detailed simulation analysis is conducted using PSCAD/EMTDC to validate the effectiveness of the developed scheme by the superior approximation performance between simulated curves and calculated curves. [ABSTRACT FROM AUTHOR]

This paper focuses on the influence of the fractional-order (FO) resonant capacitor on the zero-voltage-switching quasi-resonant converter (ZVS QRC). The FO impedance model of the capacitor is introduced to the circuit model of the ZVS QRC; hence, a piecewise smooth FO model is developed for the converter. Numerical solutions of the converter are obtained by using both the fractional Adams–Bashforth–Moulton (F-ABM) method and Oustaloup's rational approximation method. In addition, the analytical solution of the converter is obtained by the Grünwald–Letnikov (GL) definition, which reveals the influence of the FO resonant capacitor on the zero-crossing point (ZCP) and resonant state of the converter. An experimental platform was built to verify the results of the theoretical analysis and numerical calculation. [ABSTRACT FROM AUTHOR]

Capacitors are crucial components in power electronic converters, responsible for harmonic elimination, energy buffering, and voltage stabilization. However, they are also the most susceptible to damage due to their operational environment. Accurate temperature estimation of capacitors is essential for monitoring their condition and ensuring the reliability of the converter system. This paper presents a novel method for estimating the core temperature of capacitors using a long short-term memory (LSTM) algorithm. The approach incorporates a continued training mechanism to adapt to variable load conditions in converters. Experimental results demonstrate the proposed method's high accuracy and robustness, making it suitable for real-time capacitor temperature monitoring in practical applications. [ABSTRACT FROM AUTHOR]

Conventional 5-level active neutral-point-clamped (5L-ANPC) topology and state-of-the-art 5-level hybrid active neutral-point-clamped (5L-HANPC) topology are popular for inverter applications. However, their dc-link voltage utilization is limited to only 50%. With the maximum voltage level generated by only half dc-link voltage, these inverters are not capable of boosting voltage in their ac output. To resolve these drawbacks, this paper proposes a family of four novel 5-level boost-active neutral-point-clamped (5L-BANPC) inverters. Without requiring any flying capacitors, the proposed topologies can generate five voltage levels by effectively using the dc-link capacitors. The dc-link voltage utilization of the proposed 5L-BANPC inverters is twice that of the 5L-ANPC and 5L-HANPC topologies. While generating the five-level ac output voltage, natural voltage balancing of both dc-link capacitors and voltage boosting are achieved. Ease of implementation is another noteworthy merit of the proposed 5L-BANPC inverters because they can be implemented using six widely available commercial half-bridge modules without requiring a dedicated circuit design. The operation of the proposed topologies is analyzed. Experimental results are presented for verification. [ABSTRACT FROM AUTHOR]

This paper proposes a single-stage direct AC to high-frequency (HF) AC resonant converter based on LLC configuration for induction heating (IH) systems or HF applications. Unlike conventional converters for IH systems, the proposed topology converts the utility frequency to HF AC in a single stage without using a DC link inductor and capacitors and takes the advantages of LLC configuration. Additionally, it improves the power factor to 0.9–1, lowers the THD (3.2% experimentally), and protects against the high-frequency components. An embedded control scheme was designed to keep the HF current oscillating at a resonant frequency, ensuring zero-voltage switching. The operating principle of the proposed topology was investigated using mathematical equations and equivalent circuits. Finally, it was verified using computer simulation, and an experimental prototype of 1.1 kW was developed to demonstrate the proposed topology's uniqueness. [ABSTRACT FROM AUTHOR]

Three LED drivers which can be used for illumination, but whose main task is the transmission of information (data) via the light of the LEDs, are explored in this paper. The converter circuits need no capacitors for the energy transformation and avoid an inrush current. The lack of necessity of electrolytic capacitors reduces cost and space. Dimming the illumination is also easy to achieve. The control concept of the converters and the generation of pulsing of the LEDs for transmitting the information (data) are explained. The converters can also be expanded to more stages to drive more LEDs with different types of information. All three converters are explained in detail; all presented circuits are built up and simulated with LTSpice. Several data transmission concepts are applied and demonstrated through simulations. [ABSTRACT FROM AUTHOR]

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor ( K c ) can be electronically controlled by adjusting the external bias current ( I B ). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has many advantages of low switching losses, good harmonic performance and high modularity structure in state-of-the-art HVDC applications. The full-bridge submodules (FBSMs) of the hybrid MMC can inherently output negative voltage to absorb fault currents, and consequently the hybrid MMC can ride through severe DC faults without blocking. During the DC fault-ride-through process, the submodule capacitor voltage and arm current of the MMC will be temporarily increased. These characteristics limit the proportion of the FBSMs, which should not be too low and thus increase the cost and operating losses of the hybrid MMC. In this paper, an improved sorting algorithm of SM capacitor voltage is established, and a novel virtual damping control strategy is proposed that can effectively suppress the increase in submodule capacitor voltage and arm current of the hybrid MMC during the DC fault-ride-through process. By adopting this optimization control, the proportion of FBSMs can be reduced significantly without deteriorating the fault-ride-through capability or safety of the MMC. The effectiveness of the proposed control is verified by careful theoretical analysis and detailed simulation results. [ABSTRACT FROM AUTHOR]

Materials offering high energy density are currently desired to meet the increasing demand for energy storage applications, such as pulsed power devices, electric vehicles, high-frequency inverters, and so on. Particularly, ceramic-based dielectric materials have received significant attention for energy storage capacitor applications due to their outstanding properties of high power density, fast charge–discharge capabilities, and excellent temperature stability relative to batteries, electrochemical capacitors, and dielectric polymers. In this paper, we present fundamental concepts for energy storage in dielectrics, key parameters, and influence factors to enhance the energy storage performance, and we also summarize the recent progress of dielectrics, such as bulk ceramics (linear dielectrics, ferroelectrics, relaxor ferroelectrics, and anti-ferroelectrics), ceramic films, and multilayer ceramic capacitors. In addition, various strategies, such as chemical modification, grain refinement/microstructure, defect engineering, phase, local structure, domain evolution, layer thickness, stability, and electrical homogeneity, are focused on the structure–property relationship on the multiscale, which has been thoroughly addressed. Moreover, this review addresses the challenges and opportunities for future dielectric materials in energy storage capacitor applications. Overall, this review provides readers with a deeper understanding of the chemical composition, physical properties, and energy storage performance in this field of energy storage ceramic materials. [ABSTRACT FROM AUTHOR]

Reactive power compensation (RPC) is a big problem during power system operation. Parenthetically, capacitor allocation and sizing may be the only convenient solution for RPC of power systems. The loss sensitivity factor (LSF) is applied here for finding the optimum capacitor position. This paper presents quasi-oppositional fast convergence evolutionary programming (QOFCEP), fast convergence evolutionary programming (FCEP), and evolutionary programming (EP) for the optimum location and sizing of shunt capacitors in the isolated microgrid (MG) for minimizing total real power loss throughout the day with and without the demand response program (DRP). The 33-node, 69-node, and 118- node isolated MGs have been studied to authenticate the efficacy of the suggested approach. Each MG includes small hydro power plants (SHPPs), solar PV plants (SPVPs), wind turbine generators (WTGs), diesel generators (DGs), and plug-in electric vehicles (PEVs). [ABSTRACT FROM AUTHOR]

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 μ m CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

With the rapidly growing demand for clean energy and energy interconnection, there is an urgent need for rapid and high-capacity energy storage technologies to realize large-scale energy storage, transfer energy, and establish the energy internet. Supercapacitors, which have advantages such as high specific capacitance, fast charging and discharging rates, and long cycle lifetimes, are being widely used in electric vehicles, information technology, aerospace, and other fields. The performance of supercapacitors is crucially dependent on electrode materials. These can be categorized into electric double-layer capacitors and pseudocapacitors, primarily made from carbon and transition metal oxides, respectively. However, effectively monitoring the physicochemical properties of electrode materials during preparation and processing is challenging, which limits the improvement of supercapacitors' performance. Plasma materials preparation technology can effectively affect the materials preparation processing by energetic electrons, ions, free radicals, and multiple effects in plasma, which are easily manipulated by operation parameters. Therefore, plasma material preparation technology is considered a promising method to precisely monitor the physicochemical and electrochemical properties of energy storage materials and has been widely studied. This paper provides an overview of plasma materials preparation mechanisms, and details of the plasma technology application in the preparation of transition metal hybrids, carbon, and composite electrode materials, as well as a comparison with traditional methods. In conclusion, the advantages, challenges, and research directions of plasma materials preparation technology in the field of electrode materials preparation are summarized. [ABSTRACT FROM AUTHOR]

As electrochemical research undergoes rapid technological progression, the acquisition of substantial amounts of electrochemical impedance spectra (EIS) becomes increasingly feasible. Yet, this advancement introduces intricate challenges in data processing, automation, and interpretation. This paper delves into the sufficiency of unsupervised machine learning (ML) and in particular dimensionality reduction methods in decoding EIS complexities, examining its strengths, limitations, and potential pathways for optimization. As we navigated the intricacies of non‐linear dimensionality reduction, spotlighting t‐distributed stochastic neighbor embedding (t‐SNE) and uniform manifold approximation and projection (UMAP) algorithms, a pattern emerged: these techniques excel at categorizing divergent impedance spectra but show limitations when faced with analogous circuit configurations, especially those substituting a capacitor with a constant phase element. This observation not only underscores a limitation but also accentuates that unsupervised ML approaches, alone, may not fully unravel the nuances of EIS spectra. In the concluding section of our manuscript, we discuss the implications of this finding from a practical standpoint, particularly for electrochemists seeking to apply these methods in their work. [ABSTRACT FROM AUTHOR]

The paper deals with the capacitance of cylindrical two-dimensional capacitor which consists of Cartesian orthotropic dielectric material. The determination of the capacitance of capacitor with orthotropic dielectric material by a suitable coordinate transformation is reduced to the computation of capacitance of an isotropic capacitor. It is proven that the capacitance of a Cartesian orthotropic capacitor can be obtained in terms of an isotropic capacitor whose dielectric constant is the geometric mean of the dielectric constant of the orthotropic capacitor. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is a research hotspot in medium-voltage and high-voltage applications. The measurement offset error would cause an increase in the monitoring error of the submodule (SM) capacitance of the MMC, affecting the estimation accuracy of the SM capacitance monitoring. This paper proposes a capacitor monitoring strategy based on the offset error compensation, where two reasonable capacitor monitoring periods are selected in one fundamental period under the proposed voltage-balancing control (VBC) based on the virtual capacitor voltage (VCV) to compensate for the offset error impact on the capacitance monitoring. The proposed strategy can effectively eliminate the offset error impact on the capacitance monitoring, which ensures the accuracy of the SM capacitance monitoring in the MMCs. The effectiveness of the proposed monitoring strategy is confirmed by the simulations and experiments. [ABSTRACT FROM AUTHOR]

Due to the unique properties of room temperature ionic liquids (RTILs), most researchers' interest in RTIL-based electrolytes in electric double-layer capacitors (EDLCs) stems from molecular simulations, which are different from experimental scientific research fields. The knowledge of RTIL-based electrolytes in EDLCs began with a supposition obtained from the results of molecular simulations of molten salts. Furthermore, experiments and simulations were promoted and developed rapidly on this topic. In some instances, the achievements of molecular simulations are ahead of even those obtained from experiments in quantity and quality. Molecular simulations offer more information on the impacts of overscreening, quasicrowding, crowding, and underscreening for RTIL-based electrolytes than experimental studies, which can be helpful in understanding the mechanisms of EDLCs. With the advancement of experimental technology, these effects have been verified by experiments. The simulation prediction of the capacitance curve was in good agreement with the experiment for pure RTILs. For complex systems, such as RTIL–solvent mixtures and RTIL mixture systems, both molecular simulations and experiments have reported that the change in capacitance curves is not monotonous with RTIL concentrations. In addition, there are some phenomena that are difficult to explain in experiments and can be well explained through molecular simulations. Finally, experiments and molecular simulations have maintained synchronous developments in recent years, and this paper discusses their relationship and reflects on their application. [ABSTRACT FROM AUTHOR]

In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs). [ABSTRACT FROM AUTHOR]

In power engineering, the importance of maintaining a high power factor in low-voltage electrical installations is known. In power substations for industry, the usual method of coupling is to use an automatic power factor controller which connects capacitors banks (with electromagnetic contactors). Sometimes, AC reactors are connected to the phases of the capacitors banks (to reduce transient phenomena and the deforming regime), depending on the desired value of the power factor. This paper presents an analysis (more focused on experimentation) of a low-cost system for automatic regulation of the power factor with a reduction in transients and an increase in the life of contactors (eliminating the electric arc during switching on), with capacitors banks for low-voltage three-phase installations that connect the capacitors banks by means of one three-phase solid-state relay (an expensive device for a quality device; one is used for all capacitors banks) and using several electromagnetic contactors. The automatic power factor adjustment system has a controller with a microprocessor with six outputs, controlled by the phase shift between the current (measured with a current transformer proportional to the current in a bar) and the phase voltage, which is part of a system of distribution bars (L1,2,3, N) from which electrical consumers (e.g., induction motors) are supplied. To reduce transients when connecting capacitors banks, a three-phase solid-state relay and two related electromagnetic contactors are used for each capacitors bank. The automatic power factor controller is connected to two low-capacity PLCs that control the logic of connecting the capacitors banks to reduce transients. By using the proposed regulation system, a cheaper control solution is obtained compared to the use of one solid-state relay for each capacitors banks, under the conditions in which the power factor adjustment is made as in the classic solution. If twelve capacitors banks are used, the proposed installation is 22.57% cheaper than the classical power factor regulation installation. [ABSTRACT FROM AUTHOR]

This paper proposes a new generalised boost integrated multilevel inverter (MLI) with reduced components. The proposed MLI is developed by using a modified boost integrated switched capacitor unit, which provides four-level output from each cell. The operation of the proposed MLI for symmetrical 17-level operation with sinusoidal pulse width modulation & nearest level control and asymmetrical 31-level operation with NLC is explained and validated experimentally. The experimental results of static and dynamic load conditions are analysed and discussed in detail. In addition, the proposed topology is compared with recent boost MLI topologies in terms of component count, device stress, efficiency, capacitor size and cost. From the comparative study, it is evident that the proposed MLI provides features such as reduced component count, capacitors size, overall cost and improved voltage gain. [ABSTRACT FROM AUTHOR]

Today, multilevel inverters are widely utilized in various applications. Reducing the number of components in the design of these converters is one of the crucial goals so that they have less volume and cost. This paper presents a single‐source structure for a multilevel switched‐capacitor inverter with voltage boost capability. The proposed structure can generate 25 sinusoidal‐like step voltage levels with a six times amplitude increase compared to the input. This converter uses only one direct current (DC) power source, 14 switches, and four capacitors. The nearest level control switching method has been used to control the converter, create voltage levels, and select the switching modes. A comprehensive comparison has been made with other recently presented structures to demonstrate the efficiency of the proposed structure. The advantages of the proposed structure include using only one DC voltage source, the ability to increase the output voltage six times compared to the input, the use of fewer power electronics components compared to the number of voltage levels, proper efficiency, self‐balancing of capacitors, and as a result, the lower cost. The performance accuracy of the proposed converter has been simulated in the MATLAB Simulink environment and then evaluated by a laboratory prototype. [ABSTRACT FROM AUTHOR]

Active thermography using pulsed heating is a fast and reliable method for detecting flaws in composite and metallic materials. This paper analyzes the temperature decay that occurs immediately after flash heating the front surface of stainless steel specimens as a function of time, based on a novel application of the equivalent circuit approach (ECA). The temperature decay from the front surface is equated to the discharge of a capacitor. The ECA is based on the charging (temperature rise due to flash heating) of a capacitor, followed by its discharge (temperature decay) through a series of resistors (which depends on the conductivity of the material) and capacitance (which depends on the thermal capacitance of the layers) through which the heat is dissipated. The proposed approach analyzes the sequences of temperature data obtained at each pixel location during cooling from a step wedge and a specimen with multiple flat-bottom holes. Time constant maps derived from the analysis are used to ascertain the thickness of the step wedge, detect the flaws, and evaluate the remnant thickness of the flaws. A correlation has been established between the thickness and the time constants. The above approach has been used to estimate the diameter of the flat-bottom holes. [ABSTRACT FROM AUTHOR]

The issue of sub-module (SM) capacitor voltage unbalance is a hot topic in the current research into the modular multilevel converter (MMC). An excellent strategy comprises mitigating the SM capacitor voltage imbalance by adjusting the SM on time. The traditional capacitor voltage balancing control regulates the speed to maintain accuracy. A unique SM capacitor voltage balancing control strategy is presented in this paper and is based on conventional capacitor voltage balance management and neural network prediction. Firstly, the SM capacitor voltage and arm current are speculated by operating the time series forecasting technique in real time, considering the dynamic changes in the SM capacitor voltage and arm current. Secondly, the SM capacitor voltage distinction between the actual and theoretical value is determined, and a deviation's mixed Gaussian distribution is established to estimate its compensation voltage. Thirdly, the SM triggering sequence is anticipated by using the neural network along with the pilot values of the SM capacitor voltage, arm current, and the offset compensation value, and the control is executed. Finally, a three-phase, six-leg, eight-module, nine-level MMC model is built to verify the feasibility of the suggested approach. [ABSTRACT FROM AUTHOR]

The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as C n = 2 × C n − 1 , the variable capacitor C n of ADC1 can be updated to be closest to the sum of C n − 1 of ADC1 and C n − 1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the C n of ADC1 can be connected with two of the C n − 1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update C n . This process is iterated, until C n is in agreement with the sum of two of C n − 1 . Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. [ABSTRACT FROM AUTHOR]

The capacitor voltage unbalancing is the common problem in modular multilevel converter. This problem occurs even at the fundamental frequency due to the modulation technique which generates the unequal periods of the gate signals. To reduce this problem, this paper introduced a new submodule (SM)-based modular multilevel converter (MMC). The proposed MMC can generate the 2N + 1 level at the load side. By properly controlling the arm current of the converter, DC capacitor voltage in each submodule is balanced at its base voltage and improves the circulating current during unequal periods of the gate signals without using controller. This paper presents the performance of new submodule-based modular multilevel converter. Finally, the proposed converter is compared with the conventional modular multilevel converter topologies with and without third harmonic injection method. Further the proposed structure and presented techniques have been simulated in the MATLAB/SIMULINK, and the practical implementation has been done using hardware-in-the-loop (HIL) test. [ABSTRACT FROM AUTHOR]