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Improving the energy conversion efficiency of light-emitting diodes (LEDs) for blue light emission has been a continuing pursuit for the past several decades. Here, we report InGaN/GaN LEDs with improved energy efficiency through the simple deposition of multifunctional ultrathin AlN/Al 2 O 3 layers on top of p-type GaN (i.e., GaN:Mg) using remote plasma pretreatment and plasma-enhanced atomic-layer deposition (PEALD). The AlN/Al 2 O 3 stacked layers played principal roles in improving the LED energy efficiency: 1) The surface defect states of p-type GaN were reduced to minimize leakage current and oxidation was prevented by passivating the GaN surface; 2) the net positive charges formed at the AlN/GaN interface enhanced the hole injection rate into the multi-quantum well (MQW) by formation of downward band bending with the increased surface potential; and 3) the increased hole injection rate induced the band-filling effect and screening of internal polarization fields in the MQW. The AlN/Al 2 O 3 stacked layers deposited on the GaN:Mg have overall improved the radiative recombination rate of the InGaN/GaN LEDs and thus light-emission efficiency. X-ray photoelectron spectroscopy was used to characterize the surface potential change of GaN. The peak efficiency values of wall-plug efficiency, the external-quantum efficiency, and the efficacy of the AlN/Al 2 O 3 coated InGaN/GaN LEDs were improved by 29%, 29%, and 30%, respectively. The corresponding efficiency droop rates were decreased by 13%, 6% and 3%, respectively, as compared to those of reference LEDs. [ABSTRACT FROM AUTHOR]

Abstract: We report detailed results on the temperature dependence and thermal stability of the planar-integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN high-electron mobility transistors (HEMTs). Compared to the standard mesa etching technique, the plasma treatment can achieve the same device isolation results. The E/D-mode HEMTs and the corresponding digital integrated circuits fabricated by the planar process exhibit stable operation from room temperature up to 350°C. No degradation in device performance was observed after a 140-h thermal stress at 350°C, implying excellent thermal stability of the planar process. The direct-coupled FET logic inverter, realized by planar-integration of E/D-mode HEMTs, presents larger noise margins (NMS) at high temperatures than the previously reported work, demonstrating promising potential for GaN-based high-temperature digital ICs. The NM improvement can be attributed to the higher threshold voltage and the improved gate turn-on voltage of the E-mode HEMTs that is achieved with larger plasma treatment dose. [Copyright &y& Elsevier]

Highlights: [•] Propose nonalloyed Schottky-Source/Drain technology enabling a gate-first InAlN/GaN HEMTs. [•] The Schottky source can reduce source carrier injection and subthreshold leakage. [•] The gate-first InAlN/GaN HEMTs achieves 229% improvement in breakdown voltage. [•] The Schottky-Source/Drain technology is beneficial to device downscaling. [•] This gate-first InAlN/GaN HEMTs show great promise for self-aligned HEMTs. [ABSTRACT FROM AUTHOR]

Abstract: In this report, we present a study on the exploitation of nanostructure-thin film interfaces. Here, the objective is to utilize such interfaces for developing nanostructures for advanced sensing devices, while using state-of-the-art microelectronic technology that enables batch production. In this context, growth of ZnO nanostructures on the GaN/AlGaN heterostructure layers was studied. A fabrication process, based on a hydrothermal growth method, was used for preparing the interfaces of nanostructured thin film. Samples were characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM) and obtained results suggested near epitaxial quality of the hetero-interface. Field-effect transistors (FETs) based on ZnO nanorods/GaN heterostructures were fabricated and tested in a controlled gas environment. Thus, it was demonstrated that nanostructures could be exploited in unconventional ways by employing them in scalable and batch-producible conventional semiconductor devices. [Copyright &y& Elsevier]

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region''s volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (fT) of 21.4 GHz, the maximum frequency of oscillations (fmax) of 32.6 GHz and the collector–emitter breakdown voltage (BVCEO) of 5.6 V, which are the highest fT and the highest fTBVCEO product among the lateral bipolar transistors (LBTs). [Copyright &y& Elsevier]