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Next-generation memories have been actively researched to replace the existing memories like DRAM and flash in deep sub-micron process technology. Unlike the conventional charge-based memories, next-generation memories utilize the resistive properties of different materials to store and read a data. Among the next-generation memories, Phase Change Memory (PCM) is seen as a good choice for future memory systems, given its good read performance, process compatibility and scaling potential. To enhance the storage density, multi-level cell (MLC) operation is seemed promising which can store more than one bit in each PCM cell. However, MLC operation significantly degrades the reliability of PCM, thus requiring a strong Error Correction Code (ECC) to guarantee correct memory operation. The use of heavyweight ECC comes at cost of significant degradations in storage density, performance and energy efficiency. In this article, we propose a heterogeneous PCM architecture which uses both multi-level cell and single-level cell (SLC) together for a single word line. With highly-reliable SLC cells, the overall array reliability is enhanced. To improve the reliability further, a dynamic self-encoding/decoding scheme is performed before the data is written to the PCM cells. The dynamic scheme automatically determines the locations of MLC and SLC cells and sets the corresponding resistance levels to be programmed. Since the proposed encoding/decoding scheme does not require any additional stages or storages for encoding and decoding, the overhead is negligible. The improved reliability allows to use lighter ECC scheme which in turn helps to improve performance and energy efficiency of the MLC PCM. The experimental results show that the reliability is improved by approximately 106 times compared to the conventional 4LC and more than 103 times compared to the existing encoding methods. The performance improvement is 21.5 percent over the conventional 4LC and is more than 4.1 percent higher than the prior encoding techniques. The proposed method is 30.3 percent more energy efficient than the conventional 4LC and this is similar or higher than other energy efficiency improvement methods. [ABSTRACT FROM AUTHOR]

Despite hitting major roadblocks in 2-D scaling, NAND flash continues to scale in the vertical direction and dominate the commercial nonvolatile memory market. However, several emerging nonvolatile technologies are under development by major commercial foundries or are already in small volume production, motivated by storage-class memory and embedded application drivers. These include spin-transfer torque magnetic random access memory (STT-MRAM), resistive random access memory (ReRAM), phase change random access memory (PCRAM), and conductive bridge random access memory (CBRAM). Emerging memories have improved resilience to radiation effects compared to flash, which is based on storing charge, and hence may offer an expanded selection from which radiation-tolerant system designers can choose from in the future. This review discusses the material and device physics, fabrication, operational principles, and commercial status of scaled 2-D flash, 3-D flash, and emerging memory technologies. Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward the future role of emerging technologies in radiation environments. [ABSTRACT FROM AUTHOR]

This retrospective paper describes the RowHammer problem in dynamic random access memory (DRAM), which was initially introduced by Kim et al. at the ISCA 2014 Conference. RowHammer is a prime (and perhaps the first) example of how a circuit-level failure mechanism can cause a practical and widespread system security vulnerability. It is the phenomenon that repeatedly accessing a row in a modern DRAM chip causes bit flips in physically adjacent rows at consistently predictable bit locations. RowHammer is caused by a hardware failure mechanism called DRAM disturbance errors, which is a manifestation of circuit-level cell-to-cell interference in a scaled memory technology. Researchers from Google Project Zero demonstrated in 2015 that this hardware failure mechanism can be effectively exploited by user-level programs to gain kernel privileges on real systems. Many other follow-up works demonstrated other practical attacks exploiting RowHammer. In this paper, we comprehensively survey the scientific literature on RowHammer-based attacks as well as mitigation techniques to prevent RowHammer. We also discuss what other related vulnerabilities may be lurking in DRAM and other types of memories, e.g., NAND flash memory or phase change memory, that can potentially threaten the foundations of secure systems, as the memory technologies scale to higher densities. We conclude by describing and advocating a principled approach to memory reliability and security research that can enable us to better anticipate and prevent such vulnerabilities. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is a non-volatile memory device with favorable characteristics such as persistence, byte-addressability, and lower latency when compared to flash memory. However, it comprises memory cells that have limited lifetime and higher access latency than DRAM. The row buffer size of a PCM is preferred to be larger than 128B to fill the latency gap between two memories and to reduce the metadata overhead incurred by wear leveling. As the cache line size in a general-purpose processor is 64B, a read-modify-write (RMW) module is required to be placed between the processor and the PCM, which in turn induces a performance degradation. To reduce such an overhead and enhance the reliability of a device, this paper presents a new RMW architecture. The proposed model introduces a DRAM cache in the RMW module, which minimizes redundant read operations for write operations by pre-fetching the entire transaction unit instead of merely caching the 64B requested data. Furthermore, a typeless merge operation is performed with the proposed cache by gathering multiple commands accessing consecutive addresses, irrespective of whether they are READ or WRITE. Simulation results indicate that the proposed method enhances the speed by 3.2 times and the reliability by 49 percent as compared to the baseline model. [ABSTRACT FROM AUTHOR]

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance. [ABSTRACT FROM AUTHOR]

Recently, there have been approaches of using phase change memory (PCM) for the wearable devices. PCM can prolong the lifetime of the wearable devices, because it can endure approximately 108 writes per cell. Unfortunately, because previous well-known software translation algorithms were designed to use DRAM as the main memory, they execute frequent write operations on the PCM. As a solution, this paper proposes a software layer called ?load-balancing flash translation layer (Load-FTL)? that enhances the performance of the PCM-based wearable devices by efficiently identifying the hot data and managing them in the PCM. Furthermore, Load-FTL prolongs the durability of the PCM using a window-based wear-leveling algorithm. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) is a promising DRAM alternative because of its non-volatility, high density, low standby power and close-to-DRAM performance. These features make PCM an attractive solution to optimize the management of NAND flash memory in embedded systems. However, PCM's limited write endurance hinders its application in embedded systems. Therefore, how to manage flash memory with PCM—particularly guarantee PCM a reasonable lifetime—becomes a challenging issue. In this paper, we propose to partially replace DRAM using PCM to optimize the management of flash memory metadata for better system reliability in the presence of power failure and system crash. To prolong PCM's lifetime, we present a write-activity-aware PCM-assisted flash memory management scheme, called PCM-FTL. By differentiating sequential and random I/O behaviors, a novel two-level mapping mechanism and a customized wear-leveling scheme are developed to reduce writes to PCM and extend its lifetime. We evaluate PCM-FTL with a variety of general-purpose and mobile I/O workloads. Experimental results show that PCM-FTL can significantly reduce write activities and achieve an even distribution of writes in PCM with very low overhead. [ABSTRACT FROM AUTHOR]

The NAND flash memory has been widely used in computer and consumer electronic devices. A multilevel-cell (MLC) NAND flash memory allows two or more bits to be stored per cell, improving the cell density and, hence, reducing the cost. The lower price of the MLC NAND has made it appearing in both consumer product and datacenter markets. In MLC NAND, the page read latency varies according to the page type. For read-dominated workloads, placing read-intensive data into pages with longer read latencies may result in degraded read performance. In this brief, an online method called FastRead is proposed to improve the read performance of MLC NAND-based storage. The FastRead method dynamically identifies read-intensive data and migrates them to pages with shorter read latency to improve the read performance. According to the performance results, FastRead can reduce the read response time by up to 22% (17% on average) for read-dominated workloads on a Triple-level cell NAND. In addition, FastRead does not have noticeable performance impact for write-dominated workloads, and the overhead is insignificant. [ABSTRACT FROM PUBLISHER]

In multi-level-cell memory, such as flash and phase-change memory, shrinking cell size and the growing number of levels per cell worsen the access rate to capacity ratio and even reduce access rate. We present minimal maximum-level programming, a scheme for expediting cell programming by sharing physical cells among multiple data sectors and exploiting the fact that making moderate changes to a cell’s charge level is faster than making large ones. In particular, we encode the data such that in the $k$ th writing of data to a cell, only the lowest $k+1$ levels are utilized. Unlike in previously proposed cell-sharing schemes, different same-size data sectors occupy different numbers of physical cells, and a cell may hold a fraction of a bit of a given data sector. Nevertheless, the exposed sector size remains unchanged. Data are encoded, but without redundancy. In a four-level cell example, we achieve up to 75% reduction in write latency. Read latency may be degraded, depending on the percentage of utilized capacity. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) is a promising candidate as a storage medium to resolve the performance gap between main memory and storage in battery-powered mobile computing systems. However, it is more expensive than flash memory, and thus introduces a more serious storage capacity issue for low-cost solutions. This issue is further exacerbated by the fact that existing file systems are usually designed to trade space utilization for performance over block-oriented storage devices. In this work, we propose a multi-grained block management strategy to improve the space utilization of file systems over PCM-based storage systems. By utilizing the byte-addressability and fast read/write feature of PCM, a methodology is proposed to dynamically allocate multiple sizes of blocks to fit the size of each file, so as to resolve the space fragmentation issue with minimized space and management overheads. The space utilization of file systems is analyzed with consideration of block sizes. A series of experiments was conducted to evaluate the efficacy of the proposed strategy, and the results show that the proposed strategy can significantly improve the space utilization of file systems. [ABSTRACT FROM PUBLISHER]

The limited write endurance is one of the major obstacles for phase-change random access memory (PRAM)-based main memory. Traditionally, wear-leveling (WL) techniques were proposed to enhance its lifetime by balancing write traffic. However, these techniques do not concern the endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes results in lifetime degradation due to the weakest cells. In this paper, we first define a new metric-wear rate (i.e., writes/endurance) considering both the write traffic and endurance distribution from application and hardware, respectively. After investigating the writing behavior of applications and endurance variation, we propose an architecture-level leveling mechanism to balance wear rate of cells across the PRAM chip. Hardware and algorithm to support the proposed leveling mechanism are presented. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, this situation is formulated as a maximum weight perfect matching problem in bipartite graph. Thereafter, a novel algorithm that minimizes wear-rate and swapping by employing Kuhn–Munkras algorithm is proposed to maximize PRAM lifetime and minimize performance degradation. The experimental results show $\sim 17 \times $ lifetime improvement over prior WL. [ABSTRACT FROM PUBLISHER]

Phase change memory (PCM) is non-volatile memory that is byte-addressable. It is two to four times denser than DRAM, orders of magnitude better than NAND Flash memory in read latency, and 10 times better than NAND Flash memory in write endurance. However, it still limits the number of write operations to at most 10^6 times per PCM cell. To extend its lifetime, it is necessary to evenly distribute write operations over all the memory cells. Up to now, the \mathrm{B^{+}} -Tree index structure has been used to quickly locate a search key in a relational database management system (RDBMS). All the record keys in each node are sorted and packed upon insertion in, and deletion from, the \mathrm{B^{+}} -Tree. In addition, a counter keeps track of the number of valid keys in the \mathrmB^+ -Tree. Consequently, a \mathrmB^+ -Tree algorithm results in a large number of write operations, which deteriorates the endurance of PCM. This restricts the usage of PCM on a database server and deteriorates performance of database servers. In this paper, we propose a novel PCM-aware \mathrmB^+ -Tree index structure, called \mathrmPB^+ -Tree, to provide wear-leveling in PCM. According to our experiment results, \mathrmPB^+ -Tree is much faster than the existing \mathrmB^+ -Tree algorithms for PCM and NAND Flash memory with versatile workloads. More importantly, our scheme also greatly reduces the number of write operations compared to other \mathrmB^+ -Tree algorithms. All of these results suggest that \mathrmPB^+ -Tree is the \mathrmB^+ -Tree algorithm best fitted to PCM. [ABSTRACT FROM AUTHOR]

With their potential for high scalability and density, resistive memories are foreseen as a promising technology that overcomes the physical limitations confronted by charge-based DRAM and flash memory. Yet, a main burden towards the successful adoption and commercialization of resistive memories is their low cell reliability caused by process variation and limited write endurance. Typically, faulty and worn-out cells are permanently stuck at either ‘0’ or ‘1’. To overcome the challenge, a robust error correction scheme that can recover from many hard faults is required. In this paper, we propose and evaluate RDIS , a novel scheme to efficiently tolerate memory stuck-at faults. RDIS allows for the correct retrieval of data by recursively determining and efficiently keeping track of the positions of the bits that are stuck at a value different from the ones that are written, and then, at read time, by inverting the values read from those positions. RDIS is characterized by a very low probability of failure that increases slowly with the relative increase in the number of faults. Moreover, RDIS tolerates many more faults than the best existing scheme—by up to 95 percent on average at the same overhead level. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM) has been considered an attractive alternative to flash memory and DRAM. It has promising features, including non-volatile storage, byte addressability, fast read and write operations, and supports random accesses. However, there are challenges in designing algorithms for PCM-based memory systems, such as longer write latency and higher energy consumption compared to DRAM. In this paper, we propose a new predictive B \(^{+}\) -tree index, called the B \(^{p}\) -tree, which is tailored for database systems that make use of PCM. Our B \(^{p}\) -tree reduces data movements caused by tree node splits and merges that arise from insertions and deletions. This is achieved by pre-allocating space on PCM for near future data. To ensure the space are allocated where they are needed, we propose a novel predictive model to ascertain future data distribution based on the current data. In addition, as in [4], when keys are inserted into a leaf node, they are packed but need not be in sorted order. We have implemented the B \(^{p}\) -tree in PostgreSQL and evaluated it in an emulated environment. Our experimental results show that the B \(^{p}\) -tree significantly reduces the number of writes, therefore making it write and energy efficient and suitable for a PCM-like hardware environment. [ABSTRACT FROM PUBLISHER]

To satisfy the growing market demand for embedded nonvolatile memory, alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM, however, must feature high reliability during both packaging and functional stages. This paper studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set-state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is the best candidate for the storage device of next-generation mobile consumer electronics. PCM has the potential to replace NAND flash memory, due to its non-volatility, in-place programmability, and low power consumption. Even though the lifetime of PCM is longer than that of flash memory, wear leveling is still required to cope with the non-uniformity of storage workload or malicious attack. In this paper, a novel wear-leveling algorithm for PCM storage is proposed, where more physical pages are allocated to frequently updated logical pages, to balance the wear counts of PCM cells. In comparison with the previous techniques, the proposed algorithm improved the lifetime of PCM by at maximum 14 times and on average 8 times. [ABSTRACT FROM AUTHOR]

Versioning file systems are widely used in modern computer systems as they provide system recovery and old data access functions by retaining previous file system snapshots. However, existing versioning file systems do not perform well with the emerging PCM (phase-change memory) storage, because they are optimized for hard disks. Specifically, a large amount of additional writes incurred by maintaining snapshot degrades the performance of PCM seriously as write operations are the performance bottleneck of PCM. This paper presents a novel versioning file system, designed for PCM, that reduces the writing overhead of a snapshot significantly. Unlike existing versioning file systems that incur cascade writes up to the file system root, our scheme breaks the recursive update chain at the immediate parent level. The proposed file system is implemented on Linux 2.6 as a prototype. Measurement studies with various I/O benchmarks show that the proposed file system improves the I/O throughput by 144 percent on average, compared to ZFS, a representative versioning file system. [ABSTRACT FROM PUBLISHER]

Recent advance in per-cell bit density and semiconductor technology for NAND flash memories have led to significant cost reduction in non-volatile storage implementation. However, the reliability of data stored in flash memory has dramatically decreased, requiring an efficient mechanism to detect and correct bit errors during read and write operations of the data. For this purpose, when user data are often written into a flash page, an Error Correction Code (ECC) for the data is generated and stored in the spare area of the page. ECCs tend to become longer to correct more bit errors, sometimes beyond what is affordable by the spare area. In order to cope with this problem, there have been many attempts to keep ECCs in the data area, as opposed to the spare area of the flash memory. However, an additional mapping mechanism is required to locate ECCs for a given data page, and the program time and cycle are increased due to reading/storing the ECCs. In this paper, we present a novel ECC management mechanism with an assist from PCM for NAND flash storage systems. This technique uses PCM as a temporal storage to store ECCs for the data in log blocks. Later, the pages in log blocks are merged into data blocks with their ECCs kept in the PCM. Our experimental results show that the overhead from ECC management has been improved by 57% and 69% over previous attempts in BAST and FAST mapping schemes, respectively. [ABSTRACT FROM PUBLISHER]

Flash memories are currently the most widely used type of nonvolatile memories. A flash memory consists of floating-gate cells as its storage elements, where the charge level stored in a cell is used to represent data. Compared to magnetic recording and optical recording, flash memories have the unique property that the cells are programmed using an iterative procedure that monotonically shifts each cell's charge level upward toward its target value. In this paper, we model the cell as a monotonic storage channel, and explore its capacity and optimal programming. We present two optimal programming algorithms based on a few different noise models and optimization objectives. [ABSTRACT FROM AUTHOR]

Nonvolatile memories such as Flash memory, phase change memory (PCM), and magnetic random access memory (MRAM) have many desirable characteristics for embedded systems to employ them as main memory. However, there are two common challenges we need to answer before we can apply nonvolatile memory as main memory practically. First, nonvolatile memory has limited write/erase cycles compared to DRAM. Second, a write operation is slower than a read operation on nonvolatile memory. These two challenges can be answered by reducing the number of write activities on nonvolatile main memory. In this paper, we proposed two optimization techniques, write-aware scheduling and recomputation, to minimize write activities on nonvolatile memory. With the proposed techniques, we can both speed up the completion time of programs and extend nonvolatile memory's lifetime. The experimental results show that the proposed techniques can reduce the number of write activities on nonvolatile memory by 55.71% on average. Thus, the lifetime of nonvolatile memory is extended to 2.5 times as long as before on average. The completion time of programs can be reduced by 56.67% on systems with NOR Flash memory and by 47.63% on systems with NAND Flash memory on average. [ABSTRACT FROM PUBLISHER]

A key issue in nonvolatile storage is long-term data retention. This aspect is even more important in innovative storage technologies such as phase-change memory (PCM), which promises better performance and easier scalability with respect to traditional Flash memory and potential for multilevel storage. In this respect, we experimentally investigated the stability of intermediate states obtained by means of partial-SET programming. To this end, we analyzed the effects of the width and the amplitude of the programming pulses on the degradation of intermediate programmed resistance levels over time in PCM cells. Our study was carried out by considering the average behavior of an array of PCM cells, showing that data-retention properties degrade as the programming thermal stress increases. [ABSTRACT FROM AUTHOR]

We discuss non-volatile memories (NVM) for space applications. The focus will be both on technologies and devices aimed at the mainstream commercial markets and on rad-hard devices. Commercial NVMs are very attractive for space designers due to their large size (tens of Gbits), even though they have several issues related to ionizing radiation. Rad-hard NVMs offer radiation hardness, but are available only in small size (few Mbits). Most of the emphasis in this review paper will be on the current dominant technology in the mainstream market: floating gate flash memories. A comprehensive discussion of total dose and single event effects results for a wide cross section of NVMs will be presented. Finally, we will conclude with a cursory glance at other emerging non-volatile technologies. [ABSTRACT FROM AUTHOR]

GeSh nanowires (NWs) have been grown using a vapor-liquid-solid approach for the fabrication of electrically operated phase-change random access memory device. The NWs are 40-100 nm in diameter and have approximately 90% Sb for fast crystallization. Memory devices show an on/off resistance ratio of 104, reset programming current of 0.7 mA, and set programming current of 60 nA. [ABSTRACT FROM AUTHOR]

This special section is intended to address in part the advancement of techniques for novel memory architectures and organizations. Three letters were selected that cover novel techniques on MRAM as well as Flash memory. [ABSTRACT FROM PUBLISHER]