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In this article, the C – V curve shift, trap densities responsiveness, and dynamic RON of AlGaN/GaN/GaN:C (SH:C) and AlGaN/GaN/graded-AlGaN:Si/GaN:C (DH:Si/C) heterostructure Schottky barrier diodes (SBDs) have been systematically analyzed. Due to additional 3-D electrons in graded-AlGaN:Si layer, the composite 2-D–3-D channel of DH:Si/C has a higher carrier concentration. Reducing the OFF-state electric field strength through AlGaN:Si insert layer, a smaller positive shift of C – V curve is achieved under OFF-state stress. Due to the charge shielding effect of AlGaN:Si insert layer, trapping/detrapping effects in GaN:C buffer under the OFF-state stress are well suppressed. Compared with SH:C heterostructure, the trap density responsiveness of DH:Si/C heterostructure under OFF-state stress is significantly reduced. At the same time, trap density responsiveness of the upper channel is immune to OFF-state electric stress time. In addition, the proposed SBDs show lower ON-resistance with on reverse bias stress and better dynamic performance with on reverse stress time. [ABSTRACT FROM AUTHOR]

In order to further improve the electrical characteristics of AlGaN-buffer devices, we propose a new in situ SiN/AlGaN-sandwich-barrier (SWB)/GaN/Al0.05GaN high-electron mobility transistors (HEMTs). The dc, channel temperature, and RF temperature of the proposed AlGaN-buffer devices have been systematically studied and analyzed. The SWB structure can effectively reduce the peak value of the electric field, thus effectively reducing the self-heating effect and improving the breakdown characteristics. Through the channel temperature extraction method of pulsed IV and TCAD thermal simulation, the channel temperature of devices with different barrier structures is compared and analyzed, which proves that SWB structure can effectively reduce the channel temperature of devices. Due to the more obvious potential modulation effect between gate and drain, the ƒmax of device can improve more effectively with the increase of drain voltage. In addition, load-pull measurement at 10 GHz revealed that a saturated power density increased from 7.3 to 8.4 W/mm and an associated PAE increased from 24.9% to 29.4%. [ABSTRACT FROM AUTHOR]

To realize the complementary circuit on the GaN-on-Si platform, an investigation of p-channel heterostructure field-effect transistors (p-HFETs) is necessary. In this study, an analytical model for the estimation of the threshold voltage (${V}_{\text {TH}}$) for GaN-based p-HFETs was developed. In this model, the impact of polarization charges at different interfaces, the influence of interface charges at oxide/GaN interface, as well as the out-diffusion effect of Mg dopant in the p-GaN layer were all taken into consideration for systematic exploration. Herein, GaN-based p-HFETs were fabricated to verify the relationship between the ${V}_{\text {TH}}$ and the thickness of the GaN channel layer by using the proposed model. The ${V}_{\text {TH}}$ model was further confirmed through TCAD simulations. The influences of the thickness of oxide layer, Mg doping concentration in p-GaN layer, and the Al mole fraction of AlxGa $_{{1}-{x}}\text{N}$ layer on ${V}_{\text {TH}}$ were also discussed in detail. The model serves as more accurate guidance for the optimization of such p-HFETs design and complementary circuits. [ABSTRACT FROM AUTHOR]

In this work, the performance of AlGaN/ gallium nitride (GaN) high-electron mobility transistors (HEMTs) with different Fe doping tails was systematically investigated and compared. It is illustrated that the combination of the unintentionally doped (UID) GaN layer and a thinner Fe doping buffer layer would result in a faster slope rate of Fe concentration in the UID GaN layer. The devices with the fastest slope rate of Fe concentration in the UID GaN layer exhibited excellent large signal performance, including the saturated power density (${P}_{sat}$) of 9 W/mm and the power-added efficiency (PAE) of 65.6%. In addition, the ${P}_{sat}$ and the PAE of the device with the fastest slope rate of Fe concentration in UID GaN layer are 27.7% and 14.7%, which are higher than that of the device with the slowest slope rate of Fe concentration under the class AB operation conditions. Pulse ${I}$ ,– ${V}$ measurement results demonstrated that the buffer-related current collapse was more effectively suppressed in the 0.5- $\mu \text{m}$ Fe doping buffer layer because of faster slope rate of Fe concentration in UID GaN layer. Moreover, the frequency-dependent capacitance and conductance measurement results indicated that the current collapse was relevant to deep traps in the UID GaN layer introduced by Fe doping. By reducing the concentration of the deep traps caused by Fe doping, the device showed excellent characteristics of dc and RF. Furthermore, controlling the Fe doping tail was important for designing the GaN-based power amplifier with high ${P}_{sat}$ and PAE. [ABSTRACT FROM AUTHOR]

In this article, we report on the effective transconductance (gm) and gain linearity improvement of submicrometer gate AlN-barrier-based transistors using GaN/InGaN coupling-channel structures. The fabricated AlN/GaN/InGaN coupling-channel high electron mobility transistor (CC-HEMT) showed flat gm profile, greatly reduced gm derivatives, and constant dynamic source resistance compared with an AlN/GaN HEMT using the same fabrication process. The highest extrinsic current gain cutoff frequency (ƒT) of 55 GHz and the maximum oscillation frequency (ƒmax) of 80 GHz were obtained for 0.15- μm gate-length transistors, both of which remain constant values across wide input voltage (VGS) of 4 V. Moreover, a significant theoretical OIP3 value boost by 7.1 dB has been observed using the CC-HEMT as compared to the AlN/GaN HEMT. The superior linearity performance of the CC-HEMT can be attributed to the strong channel-to-channel coupling effect. The drain bias-dependence of gm, ƒT, and ƒmax versus VGS profiles illustrate that the linearity characteristics of the CC-HEMT greatly improve with an increase in VDS. These results demonstrate the AlN/GaN/InGaN material system as a viable platform for high frequency requiring high-linearity applications. [ABSTRACT FROM AUTHOR]

In this paper, AlGaN/GaN Fin-HEMTs with different fin configurations are theoretically and experimentally investigated. A simple physical-based threshold voltage model for AlGaN/GaN Fin-HEMTs is built for qualitative analysis. It is shown that the threshold voltage of AlGaN/GaN Fin-HEMTs depends on the width and height of the fin structure. The peak value and linearity of transconductance and current gain cutoff frequency are improved by reducing the fin length. It is also found that the linearity of transconductance is sensitive to the fin height, which can be attributed to the capacitance control from sidewalls. [ABSTRACT FROM AUTHOR]

A hybrid Schottky–ohmic drain technology for millimeter-wave (mmW) AlGaN/GaN high-electron-mobility transistors (HEMTs) is proposed. The Schottky metal extension in the ohmic region of drain reduces the actual source–drain spacing, resulting in a smaller ON-resistance and a higher maximum current. Extended Schottky metal in the drain region modulates the electric-field distribution, thereby leading to an improved breakdown voltage, suppressed current collapse, and high reliability. Compared with the ohmic drain, the current gain cutoff frequency (${f}_{T}$) was improved from 64 to 76 GHz, and the maximum oscillation frequency (${f}_{\text {max}}$) was improved from 125 to 157 GHz, resulting from the decreased parasitic drain resistance (${R}_{d}$). Moreover, large-signal measurements in continuous wave (CW) at 30 GHz demonstrated a peak power-added efficiency (PAE) of 45.5% and a saturated output power density (${P}_{\text {sat}}$) of 8.5 W/mm at ${V}_{\text {ds}}= {30}$ V. In addition, the direct current (DC) and radio frequency (RF) characteristics showed a negligible degradation after large-signal measurements at 30 GHz. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Si-rich SiN/Si3N4 bilayer passivation were studied in this article. The use of a Si-rich SiN interlayer leads to improved channel transport property, current collapse, power performance, and temperature-dependent stability. Devices without Si-rich SiN interlayer passivation exhibit an increase in the gate leakage current by over three orders of magnitudes with temperature increasing from 300 to 420 K, leading to an increase in a current collapse from 9.7% to 24.7%, while the devices with Si-rich SiN passivation exhibit a weak temperature dependence of leakage current and a constant current collapse about 5%. Small signal characterization shows that Si-rich SiN passivation results in a remarkable decrease in the effective gate length by ~15% with temperature up to 420 K. At 17 GHz, devices with Si-rich SiN interlayer passivation exhibit an output power density of 7 W/mm and a peak power-added efficiency (PAE) of 56%. The improved power performance of devices using Si-rich SiN interlayer passivation is attributed to the suppressed current collapse and superior device stability under high channel temperature. [ABSTRACT FROM AUTHOR]

The submicrometer gate HEMT is fabricated with an ultrathin-barrier (UTB) AlGaN/gallium nitride (GaN) combined with in situ SiN passivation. The sheet resistance of the UTB Al0.2Ga0.8N (4 nm)/GaN heterostructure is effectively reduced by the SiNx passivation layer grown by metal organic chemical vapor deposition (MOCVD), from 6500 to $312~ \Omega $ /⬜. With the 20-nm stress-engineered in situ SiN, the device not only provides a large output current of 1.05 A/mm but also demonstrates promising potential on the RF applications, which gives AlGaN material two records high cutoff frequency ${f} _{\text {T}}/{f} _{\text {max}}$ of 157 GHz/334 GHz for 100-nm gated device and 211 GHz/379 GHz for 70-nm gated device. During the continuous wave (CW) power measurement at 30 GHz, the 70-nm devices exhibit a large output power of 4.6 W/mm associated with a peak power-added efficiency (PAE) of 48.1% and a gain of 11.6 dB (${V} _{\text {ds}} =20$ V), and a high PAE of 53.8% with an output power density of 1.9 W/mm and a gain of 10.8 dB (${V} _{\text {ds}} =10$ V), respectively. The huge potential of the UTB-AlGaN/GaN is demonstrated for high-frequency and large-output power applications when it is combined with the in situ SiN, which is necessary for future communication systems. [ABSTRACT FROM AUTHOR]

In this article, we report on the high dc and RF performance of AlGaN/GaN high electron mobility transistors that employ Ti/Au/Al/Ni/Au metallization stack with shallow trench etching ohmic contact (STEOC). An excellent ohmic contact performance including low contact resistance (${R}_{C}$) of $0.28~\Omega \cdot $ mm and smooth surface morphology have been achieved simultaneously. Atomic force microscope (AFM) reveals a highly smooth surface morphology with a root mean square (rms) roughness of 6.3 nm even after 810 °C high-temperature annealing (HTA), achieving an improvement of 79% as compared to the conventional Ti/Al/Ni/Au ohmic contact (COC). A high-resolution transmission electron microscope (HRTEM) showed a glossy morphology with a continuous and uniform TiN layer formed in the interface for the STEOC sample, while a bumpy morphology caused from the Ni-Al complexes balling up and TiN island penetrating into the AlGaN/GaN heterostructure were observed for the conventional sample. Consequently, the fabricated transistors with the STEOC process show a high output current of 1.52 A/mm and low ON-resistance (${R}_{ \mathrm{ ON}}$) of $2.09~\Omega $ mm. In addition, a high current cutoff frequency (${f}_{T}$) of 60 GHz and maximum oscillation frequency (${f}_{\text {max}}$) of 150 GHz were obtained for the STEOC HEMT with a gate length (${L}_{\text {g}}$) of 150 nm. Sub-6 GHz continuous-wave mode power sweep measurements deliver a high power-added-efficiency (PAE) of 67%. These results show the significant potential of the STEOC process to facilitate the development of GaN-based power amplifier (PA) applied for 5G. [ABSTRACT FROM AUTHOR]

The gate and drain bias dependence of hot electron-induced degradation in GaN-based metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) was investigated in this work. Devices exhibit an abnormal increase in peak transconductance (${G}_{m}$ ,max) during hot carrier stress (HCS) and a partially quick recovery of that after removing the electrical stress. A physical model is proposed to explain the abnormal electrical characteristics caused by HCS. By using density functional theory (DFT), we calculated the energy for electrons to dehydrogenate preexisting [NGaH3]−1 complexes in GaN layer during stress. The dehydrogenation of defects affects the Gm,max of devices. Meanwhile, the neutralization of donor traps in AlGaN barrier layer also plays a significant role in the increase of Gm,max and the detrapping effect of electrons from these traps after removing the electrical stress accounts for the partially quick recovery of ${G}_{m, \text{max}}$. [ABSTRACT FROM AUTHOR]

In this letter, we explore the impact of configuration parameters for Fin-like high-electron-mobility transistors (HEMTs) formed by partially etching barrier under the gate on improving transconductance (Gm) and cutoff frequency (ƒT) linearity. It is found that the Gm profile for Fin-like HEMTs can be optimized by choosing appropriate device parameters, including the etching depth (HR) and width (WR) of recess region, as well as the duty ratio (α) of the planar elements in a periodic unit along the gate width. In general, not only does WR affect the gate voltage swing (GVS) but also HR and α have an important role in Gm profile flatness. In addition, the fabricated Fin-like HEMTs shows a GVS of the transconductance plateau larger than 5.6 V and a constant ƒT/ƒmax of 45 GHz/65 GHz over a wide gate voltage range. Furthermore, the proposed architecture also features an exceptional linearity performance at 8 GHz with an output third-order intercept point (OIP3) of 38.5 dBm, whereas that of the planar HEMT is 31 dBm. The device demonstrated in this article has great potential to be a new paradigm for future wireless communication systems where high linearity is essential. [ABSTRACT FROM AUTHOR]

We studied how irradiation with fast (14 MeV) and thermal (<0.4 eV) neutrons affected the properties of GaN PIN diodes, measuring their I-V characteristics before and after irradiation. Irradiation with fast neutrons caused the carrier removal effect when the reverse bias was low. Irradiation with thermal neutrons significantly increased the reverse-bias current, possibly because of damage to the passivation layer, defects induced in the GaN, and defects near the metal/GaN interface acting as tunneling sites. However, the forward current decreased both after fast neutron radiation and after thermal neutron radiation. Irradiation with thermal neutrons destroyed the SiO2 passivation layer. The crystal quality and optical properties of the GaN PIN diodes were characterized by examining changes in the photoluminescence (PL) and micro-Raman scattering spectra. As the fluence of neutrons increased, the yellow luminescence (YL) intensity increased because of the increase in \text V\mathrm {{Ga}} -related defects. Irradiation with fast and thermal neutrons destroyed the lattice integrity and changed the strain state of the devices, which was the main reason for the shift in the \text E\mathrm {{2}}^{\mathrm {{high}}} phonon mode. [ABSTRACT FROM PUBLISHER]