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A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]

An all-digital sliding-mode (ADSM) controlled dc-dc converter, utilizing single-bit oversampled frequency domain digitizers in its feedback path is proposed. Sliding-mode control provides several benefits over the traditional PID control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. However, analog implementations of sliding-mode control require several amplifiers in the controller and suffer from process, voltage, and temperature variations. In the proposed approach, the sliding-mode controller (SMC) is implemented digitally; utilizing a first order single-bit ΣΔ frequency to digital converter (ΣΔFDC)-based feedback and reference digitizing ADCs, running at 32-MHz sampling rate. The ADSM regulator achieves 1% settling time in less than 5 μs for a load variation of 600 mA. The SMC uses a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady-state error (or dc offset), and band limits the switching frequency, which are the two common problems associated with SMCs. The IC is designed and fabricated on a 0.35-μm CMOS process occupying an active area of 2.72 mm2. [ABSTRACT FROM AUTHOR]

The design and analysis of a fully integrated multi-stage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 μim SiGe RFBiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA. [ABSTRACT FROM AUTHOR]

Wideband low-noise ΣΔ fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop non-linear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time-voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order ΣΔ modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-μm CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled. [ABSTRACT FROM AUTHOR]

An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power. [ABSTRACT FROM PUBLISHER]

Efficient current, voltage, and power sensing are critical blocks for power management, switching regulators, maximum power point tracking (MPPT) circuit, and motor control. This paper presents a standard CMOS and low-power current-to-digital converter (IDC) that senses the current flowing at high-voltage nodes. The proposed sensor uses a CMOS-switched capacitor circuit to sense a dc–dc converter output current and gives digital output without an analog-to-digital converter (ADC), or the need for high-voltage technologies. Compared to the resistor-based current-sensing methods that require current-to-voltage circuit, gain block, and an ADC converter, the proposed sensor is a low-power integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 5 V, 0.7 μm, and three metal CMOS technology and occupied less than 10% area (1 mm2 area) compared to other sensors. It consumes 18 mW that is less than 40% power consumed by other sensors, and its current measurement error is below 0.4%. The proposed IDC circuit has been characterized as standalone and with a boost dc–dc regulator and MPPT for photovoltaic systems. [ABSTRACT FROM AUTHOR]

A noise-shaped direct digital IF to RF (DIF2RF) DAC with embedded upconverter mixer is presented. The digital IF signal is noise shaped by a bandpass Σ-Δ modulator with 1-bit IF output followed by a semidigital finite impulse response (FIR) filter. The current mode FIR filter combines scaled values of the local oscillator (LO) signal for performing reconstruction filtering and upconversion in a single module. The DIF2RF design modulates the digital IF signal with a digital LO signal. This topology eliminates the transconductance nonlinearity of conventional mixers and is inherently linear due to single-bit digital IF input. The presented architecture reduces clock jitter sensitivity of 1-bit DACs by masking IF clock transitions with LO signals. A prototype of the DIF2RF DAC is designed and fabricated in a five-layer metal 0.25-μm digital CMOS process. The architecture can be used in low-power software-defined digital-IF transmitters. The DIF2RF DAC consumes 49 mA from a 2.5-V supply, achieving -64.7-dBc third-order intermodulation at 1.03 GHz with a spurious-free dynamic range of 72 dB in a 15-MHz bandwidth. [ABSTRACT FROM AUTHOR]

Pulsewidth modulation (PWM) and sigma-delta modulation (SDM) have been used in several high linearity, high accuracy power delivery applications such as dc-dc power converters, audio, and radio frequency power amplifiers and data converters. While PWM can generate high linearity signals with high efficiency, it suffers from discrete tonal output spectrums. SDM, on the other hand, can generate high linearity output spectrums with shaped quantization noise spectrums and lower efficiencies due to oversampling requirements. In this paper we present a particular class of carrier frequency modulated PWM (CFMPWM), which spreads the tonal content of regular PWM uniformly in frequency and reduces the baseband noise with respect to SDM by up to 15 dB. The new modulation scheme preserves the high efficiency properties of PWM. An approximate method to estimate the spectrum of CFMPWM signals with both deterministic and random modulation is also presented. Simulation results and experimental data are reported to analyze the spectral spreading properties of the proposed CFMPWM scheme. [ABSTRACT FROM AUTHOR]

Frequency synthesizers are fundamental building blocks in radio frequency, communications, and analog signal processing for generating high accuracy oscillatory signals. In general, the frequency synthesizer is the most sensitive block in the system since many of the signal processing elements such as clock, filters, and up/down converters depend on the synthesizer generating a clean sinusoidal signal at the given frequency. For radiation environments, the response and the sensitivity of the phase-lock loop (PLL) and the synthesizer block is very critical. This paper examines the effect of single events (SEE) radiation on the PLL locking and steady state response. The PLL circuits operating at 2.4 GHZ were designed and fabricated using a 0.13 μm CMOS process This paper presents the experimental and simulations results on the SEE radiation effects on the PLL. [ABSTRACT FROM AUTHOR]

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components. [ABSTRACT FROM AUTHOR]

A radiation-tolerant digital multiphase current-mode hysteretic point-of-load regulator fabricated on a commercial 180-nm CMOS process is presented. Experiments and simulations are used to demonstrate its single-event immunity and its total-dose tolerance over 100 krad(Si). Key electrical performance parameters are: 5-V input, 0.8–3.3 V output, 10-A load current, 93% peak efficiency, four-phase hysteretic quasi-current-mode buck converter with ±1.5% frequency synchronization, ±3.6% current sharing error, and 1% ripple. [ABSTRACT FROM AUTHOR]

Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phase-locked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from $95.3\;\mu {{\rm{V}}_{{\rm{RMS}}}}$ down to $14.8\;\mu {{\rm{V}}_{{\rm{RMS}}}} . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40\;\mu \rmA . It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1–3.3 V. Fabricated in a 0.25\;\mu \rmm CMOS process, the LDO core occupies an area of 0.18 mm2. [ABSTRACT FROM AUTHOR]

A novel backgate modulation technique alleviating limitations associated with supply-regulated polar transmitters is proposed. The backgate of a partially depleted silicon-on-insulator metal–semiconductor field-effect transistor with a breakdown voltage of 15 V is used to modulate the gain and output power of an RF power amplifier (PA). The high-impedance backgate provides high-efficiency and wide-dynamic-range modulation of PA gain. Measured results at 1.8 GHz demonstrate 16% power-added efficiency improvement at 6-dB backed-off output power, compared with the same RF PA without backgate modulation. [ABSTRACT FROM AUTHOR]

This paper presents a digitally controlled programmable point-of-load regulator for next-generation power systems. A novel digital control scheme was designed to minimize single-event effect (SEE)-induced transient effects. By effectively programming the loop transmission, the POL can trade off transient response time with SET robustness. The IC works with 1 to 5.5 V input voltage, 1–4.5V regulated output voltage, high efficiency (peak efficiency at 94%) and power of up to 5 W. The design was fabricated in the AMI i2t100 0.7 \mum complimentary, metal-oxide semiconductor (CMOS) process and characterized with the Jet Propulsion Laboratory (JPL) pulsed laser system. [ABSTRACT FROM PUBLISHER]

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrial–scientific–medical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit \Sigma \Delta frequency discriminator in the feedback path and a noise-cancelling \Sigma \Delta phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400–410-MHz band. A worst case near-integer spur of -\62 dBc and a phase noise of -\83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a \0.18-\mu\ m CMOS process, occupying a \ 0.14-mm^2 die area, with a quiescent current consumption of \700~\mu\ A. [ABSTRACT FROM AUTHOR]

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) reception, and transmission, respectively. A common antenna interface is reused in the three subsystems, reducing circuit complexity and number of external components. Super-regenerative architecture is used for wake-up reception, and gm-boosted common-gate stages are used to optimize receiver (RX) performance with low power consumption. The transmitter employs an all-digital frequency-locked loop to directly drive a class AB power amplifier. The transmitter can alternatively use an injection-locked power oscillator for lower bit rates and power consumption. The integrated circuit is designed and fabricated on a 0.18-\mu\m CMOS process. The wake-up RX achieves a -80-dBm sensitivity for a 50-kb/s signal and a 280-\mu\W dissipation. The BFSK RX achieves a -97-dBm sensitivity for a 75-kb/s signal and a 2-mW power consumption. Finally, the transmitter achieves an output power of -5 dBm for a power consumption of 2.9 mW. [ABSTRACT FROM AUTHOR]

A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 \mum fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented. [ABSTRACT FROM AUTHOR]

Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-μm SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB and a frequency range of 880–915 MHz. The amplifiers use switch-mode dc-dc buck converters for supply modulation, where sigma-delta (ΣΔM), delta (ΔM), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that AM gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F linearized amplifiers' output spectra at 400-kHz offset are -54 and -57 dBc, respectively. [ABSTRACT FROM AUTHOR]