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The dual-deck architecture with aligned upper and lower decks is considered a promising technology to meet the demand of increasing word-line (WL) layers of 3D NAND flash. However, the relevant reliability studies are still lacking for the dual-deck 3D NAND array. In this work, it is reported an abnormal program disturbance phenomena of the bottom WLs in the upper-deck, and the physical mechanisms were studied. According to experimental analysis and TCAD simulations, the un-programmed dummy WLs at the joint region can introduce excessive joint residual electrons in the channel before the program, resulting in insufficient channel self-boosting potential, which is responsible for the degraded program disturbance. Thus, a novel program scheme is proposed to alleviate the program disturbance, which has been validated by experiments. [ABSTRACT FROM AUTHOR]

The repeaters in cascade structure can be used to suppress the cross coupling between the nonadjacent repeaters in multiload inductive power transfer (ML-IPT) system. In this article, the cascade repeaters used in the ML-IPT system work both as power transmitters and load carriers. Based on the cascade scheme, the system models of two ML-IPT systems with single-excitation (SE) scheme for different load position are established and high-order compensations are designed to achieve constant load currents. Referring to the topologies of the two ML-IPT systems with SE scheme, a bilateral-excitation (BE) scheme is further proposed to improve output currents and system reliability, and the comparison of the conventional scheme and the proposed scheme is also presented. Finally, a prototype of ML-IPT system with the proposed BE scheme is built, where the maximum deviation of the output currents is less than 13% and the maximum power transfer efficiency reaches 89.2% for an eight-load case. [ABSTRACT FROM AUTHOR]

This paper presents a multi-period frame transient switching control (MP-TSC) scheme for buck converter with a controlled coupled inductor, aiming at improving the load transient response. The proposed buck converter utilizes a controlled coupled inductor as the output inductor. During a load transient, the coupled inductor is controlled as a small equivalent inductance so as to achieve fast transient regulation. While in the steady state, the coupled inductor behaves as a large inductance to reduce the output current ripple. Furthermore, on the basis of the proposed variable inductance circuit, an MP-TSC control scheme is proposed and implemented in a digital form. With the proposed control scheme, the load transient event is divided into n + 1 sub-periods, and in each sub-period, the capacitor-charge balance principle is used to determine the switching time sequence. Moreover, the control principle design and transient response index analysis are provided. Furthermore, its feasibility is validated in simulation and experiment with a 12–3.3V low-voltage high-current synchronous buck converter. Experimental results demonstrate that the voltage deviation of the proposed MP-TSC scheme (coupled coefficient of the controlled coupled inductor is 0.52) has improved by more than 79% compared to that with the auxiliary circuit disabled. [ABSTRACT FROM AUTHOR]

In this paper, a sequence switching control (SSC) scheme based on an auxiliary parallel inductor is proposed to improve the transient performance of buck converters. The proposed SSC scheme introduces a small controlled inductor in parallel with the output inductor, so as to increase the inductor-current slew rate when it is activated during a load transient. Furthermore, an “n+ 1” sequence switching strategy is proposed to control the auxiliary parallel inductor. The proposed scheme divides the transient event inton+ 1 periods. In the formernperiods, the same small output voltage deviations are designed, while in the last period, a smaller deviation is done for a smooth transition from the transient to the steady state. The switching sequence is derived applying the capacitor–charge balance principle for each ofn+ 1 periods. For a given buck converter in the experiment, the settling time and the output voltage deviation of the proposed SSC scheme enhance more than 50% and 67%, respectively, over those of the time-optimal control for a 3-A load step. [ABSTRACT FROM AUTHOR]

As for ripple-current mode control, it cannot achieve average current tracking, resulting in poor current accuracy and even current waveform distortion. Meanwhile, fast-scale instability may occur in some operating conditions. To solve these problems effectively, a current-ripple compensation (CRC) control technique is proposed in this paper. The error between the average of the controlled current and the reference current is compensated by certain compensation signal, achieving average current tracking while suppressing fast-scale instability. On this basis, the compensator in the outer-voltage loop is further simplified to a proportional part by introducing a rebuilt average reference current. The idea and design procedure of the proposed CRC control technique are discussed in detail. Accordingly, two available implementation schemes for the proposed CRC are presented, including slope compensated and parabolic compensated schemes. Finally, two application cases, respectively, to dc–dc Buck converter and Boost PFC converter, are presented to verify the proposed CRC control technique. [ABSTRACT FROM PUBLISHER]