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The operating region of the modular multilevel converter (MMC) is limited by the maximum-allowable voltage ripple of cells, which is associated with the arm energy variation. Injecting the controlled second-order harmonic component into the circulating current can reduce energy variation of the arm and, thus, extend the operating region of MMC. Care must be taken, however, that the second-order circulating current affects the arm current, and inappropriately injected harmonic current may cause an undesirable arm current polarity change. Therefore, this paper first investigates and proposes the maximum-allowable second-order circulating current for extending the operating region reliably and efficiently. The active and reactive power capability of MMC is further elaborated and illustrated in line with the maximum excess energy capability for two cases, running with: 1) the original operating region and 2) the extended operating region. Finally, the P-Q diagrams for contingent operating conditions with faulty or disabled submodules are presented. Understanding the unique shape and change of P-Q capability with credible submodule failure contingency should be crucial for planning MMC-HVDC lines, and determining the energy requirements and the level of redundancy in submodules properly in order to achieve the envisioned benefits of the new HVDC. The efficacy and accuracy of the research findings are validated for the MMC-HVDC system using PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

Utilizing pulsed-latches in circuit designs is one emerging solution to timing improvements. Pulsed-latches, driven by a brief clock signal generated from pulse generators, possess superior design parameters over flip-flops. If the pulse generator and pulsed-latches are not placed properly, however, pulse-width degradations at pulsed-latches and thus timing violations might occur. In this paper, we present a unified placement framework for pulsed-latches to maintain the timing integrity. Our new placer has the following distinguished features: 1) a multilevel analytical placement framework to effectively prevent the potential pulse-width distortion problem; 2) a physical-location aware pulse-generator insertion algorithm to identify each desired group of a pulse generator and latches; and 3) a new optimization gradient for global placement to consider the impact of load capacitance of generators. Experimental results show that our placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows. [ABSTRACT FROM AUTHOR]

Pulsed-latch circuits, in which latches are triggered by a short pulse, can reduce power consumption as well as increasing performance; and they can largely be designed using conventional computer-aided design tools. We explore the automatic synthesis of clock-gating logic for pulsed-latch circuits in which gating is implemented by enabling and disabling several pulse generators. The key problem is to arrange that each group of latches contains physically close latches, so that a short pulse from a pulse generator is delivered safely, and to ensure that the latches in a group have similar Boolean gating conditions because their clock is gated and ungated together. The resulting gating conditions should be implemented using as little extra logic as possible; for this purpose we rely on Boolean division, with an internal node of existing logic being used as the divisor. The proposed clock gating synthesis is assessed in 45-nm technology. [ABSTRACT FROM PUBLISHER]