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The computer industry was a vivid place in the 1980s. IT systems and technologies thrived, and the market offered ever better, smaller, and more useful machines. Innovative technical solutions or intelligent designs that satisfied customers' needs are often listed as computer hardware milestones. Consequently, they became a permanent part of the computerisation history and can be considered hardware heritage artefacts. The purpose of the paper is to analyse the usability of selected portable computer systems. The foundation of the work is a literature review that includes technical specifications, industry reviews, and research papers. Archival materials were obtained from the Internet Archive. Studies have revealed that the main problems design engineers of portable computers had to tackle in the 1980s were the reduction of mass and size of the computer system, portable power (self-power), and the quality of the displayed image. [ABSTRACT FROM AUTHOR]

Despite a widely-acknowledged shortage of software developers, and reports of a gap between industry needs and software education, the possible gap between students' needs and software development education has not been explored in detail. In their university education, students want to take courses and carry out projects that clearly relate to their lives and their goals. This paper reports on a quantitative study of 297 software development students. The analysis of the results suggests that software development education has a predominantly social relevance to students and also has moderate personal and professional relevance. The following approaches are recommended to improve students' views of the relevance of software development education: use various learning environments; pay special attention to female students, students who did not have IT as a school subject, and students who rate their own academic performance as low; update educators on the latest developments; design programs to appeal to students and to meet societal demands. [ABSTRACT FROM PUBLISHER]

Information about upcoming events of interest to Computer Society members. [ABSTRACT FROM PUBLISHER]

Abstract: Current Web service technology is evolving towards a simpler approach to define Web service APIs that challenges the assumptions made by existing languages for Web service composition. RESTful Web services introduce a new kind of abstraction, the resource, which does not fit well with the message-oriented paradigm of the Web service description language (WSDL). RESTful Web services are thus hard to compose using the Business Process Execution Language (WS-BPEL), due to its tight coupling to WSDL. The goal of the BPEL for REST extensions presented in this paper is twofold. First, we aim to enable the composition of both RESTful Web services and traditional Web services from within the same process-oriented service composition language. Second, we show how to publish a BPEL process as a RESTful Web service, by exposing selected parts of its execution state using the REST interaction primitives. We include a detailed example on how BPEL for REST can be applied to orchestrate a RESTful e-Commerce scenario and discuss how the proposed extensions affect the architecture of a process execution engine. [Copyright &y& Elsevier]

France, the United Kingdom, and the Soviet Union implemented various public policies designed to promote the development of local computer industries, beginning in the late 1940s, that had mixed results but were part of a larger pan-European interest in promoting national economic development through the use of technologies. [ABSTRACT FROM AUTHOR]

The article focuses on the problem concerning the Linpack Benchmark 1.0 matrix generator. It examines the ability of the matrix generator in generating matrices with identical columns. It discusses the production of a matrix by the generator with at least two identical columns through defining S as the set of all integers. It explores the establishment of a pseudo-random matrix by Linpack Benchmark. Furthermore, it describes the characteristics of matrix sizes in which the matrix generator has created a matrix with identical columns.

The article discusses the impact of the computer industry on the environment, examining how the industry is attempting to reduce its footprint on the planet. Landfills are being filled up with discarded computer equipment, the author states. Of the three areas within the computer industry that touch the environment, disposal, manufacturing, and operations, it is the operational sector that has made the most visible improvements, that article indicates. Other topics include the power consumption of computers, decreasing the use of toxic substances in computers, and the disposal of unwanted equipment.

We present an approach to the analysis and optimisation of heterogeneous multiprocessor embedded systems. The systems are heterogeneous not only in terms of hardware components, but also in terms of communication protocols and scheduling policies. When several scheduling policies share a resource, they are organised in a hierarchy. In this paper, we first develop a holistic scheduling and schedulability analysis that determines the timing properties of a hierarchically scheduled system. Second, we address design problems that are characteristic to such hierarchically scheduled systems: assignment of scheduling policies to tasks, mapping of tasks to hardware components, and the scheduling of the activities. We also present several algorithms for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilisation of the system. The developed algorithms are evaluated using extensive experiments and a real-life example. [ABSTRACT FROM AUTHOR]

Multicore processors have been utilized in embedded systems and general computing applications for some time. However, these multicore chips execute multiple applications concurrently, with each core carrying out a particular task in the system. Such systems can be found in gaming, automotive real-time systems and video / image encoding devices. These system are commonly deployed to overcome deadline misses, which are primarily due to overloading of a single multitasking core. In this paper, we explore the use of multiple cores for a single application, as opposed to multiple applications executing in a parallel fashion. A single application is parallelized using two different methods: one, a master-slave model; and two, a sequential pipeline model. The systems were implemented using Tensilica’s Xtensa LX processors with queues as the means of communications between two cores. In a master-slave model, we utilized a course grained approach whereby a main core distributes the workload to the remaining cores and reads the processed data before writing the results back to file. In the pipeline model, a lower granularity is used. The application is partitioned into multiple sequential blocks; each block representing a stage in a sequential pipeline. For both models we applied a number of differing configurations ranging from a single core to a nine-core system. We found that without any optimization for the seven core system, the sequential pipeline approach has a more efficient area usage, with an area increase to speedup ratio of 1.83 compared to the master-slave approach of 4.34. With selective optimization in the pipeline approach, we obtained speed ups of up to 4.6 × while with an area increase of only 3.1 × (area increase to speedup ratio of just 0.68). [ABSTRACT FROM AUTHOR]

When accompanied by the appropriate algorithmic approach, seismic imaging is an application that can take advantage of massively parallel computer systems. Three-dimensional (3D) pre-stack time migration (PSTM) and pre-stack depth migration (PSDM) are key components of seismic imaging and require very large computing resources. In this paper, we show that execution of these algorithms can be dramatically accelerated by massive parallelism. Many oil exploration and service companies purchase supercomputing clusters for performing 3D PSTM and PSDM seismic imaging. The common azimuth migration (CAM) algorithm, ported to many architectures, is particularly well suited to offshore marine applications. This paper describes the porting of the CAM algorithm to the IBM Blue Gene/L™ supercomputer, which requires introducing a second level of parallelism, building a parallel 3D-FFT (fast Fourier transform) routine, optimizing a tri-diagonal solver for SIMD (single-instruction, multiple-data) floating-point units, and addressing various I/O concerns. We present results obtained by using up to 16,368 processors for actual data provided from a marine seismic acquisition. Finally, we provide recommendations for porting other pre-stack algorithms to a massively parallel environment. [ABSTRACT FROM AUTHOR]

The Peer-to-Peer (P2P) model, being widely adopted in today's Internet computing, suffers from the problem of topology mismatch between the overlay networks and the underlying physical network. Traditional topology optimization techniques identify physically closer nodes to connect as overlay neighbors, but could significantly shrink the search scope. Recent efforts have been made to address the mismatch problem without sacrificing the search scope, but they either need time synchronization among peers or have a low convergent speed. In this paper, we propose a scalable bipartite overlay (SBO) scheme to optimize the overlay topology by identifying and replacing the mismatched connections. In SBO, we employ an efficient strategy for distributing optimization tasks in peers with different colors. We conducted comprehensive simulations to evaluate this design. The results show that SBO achieves approximately 85 percent of reduction on traffic cost and about 60 percent of reduction on query response time. Our comparisons with previous approaches to address the topology mismatch problem have shown that SBO can achieve a fast convergent speed, without the need of time synchronization among peers. [ABSTRACT FROM AUTHOR]

Sequence alignment is a common and often repeated task in molecular biology. Typical alignment operations consist of finding similarities between a pair of sequences (pairwise sequence alignment) or a family of sequences (multiple sequence alignment). The need for speeding up this treatment comes from the rapid growth rate of biological sequence databases: Every year their size increases by a factor of 1.5 to 2. In this paper we present a new approach to high-performance biological sequence alignment based on commodity PC graphics hardware. Using modern graphics processing units (GPUs) for high-performance computing is facilitated by their enhanced programmability and motivated by their attractive price/performance ratio and incredible growth in speed. To derive an efficient mapping onto this type of architecture, we have reformulated dynamic-programming-based alignment algorithms as streaming algorithms in terms of computer graphics primitives. Our experimental results show that the GPU-based approach allows speedups of more than one order of magnitude with respect to optimized CPU implementations. [ABSTRACT FROM AUTHOR]

The use of space filling curves for proximity-improving mappings is well known and has found many useful applications in parallel computing. Such curves permit a linear array to be mapped onto a 2D (respectively, 3D) structure such that points that are distance d apart in the linear array are distance O(d½) (O(d½)) apart in the 2D (3D) array and vice versa. We extend the concept of space filling curves to space filling surfaces and show how these surfaces lead to mappings from 20 to 3D so that points at distance d½ on the 2D surface are mapped to points at distance O(d½) in the 3D volume. Three classes of surfaces, associated respectively with the Peano curve, Sierpiriski carpet, and the Hilbert curve, are presented. A methodology for using these surfaces to map from 2D to 3D is developed. These results permit efficient execution of 2D computations on processors interconnected in a 3D grid. The space filling surfaces proposed by us are the first such fractal objects to be formally defined and are thus also of intrinsic interest in the context of fractal geometry. [ABSTRACT FROM AUTHOR]

The article describes the PWRficient processors developed by P.A. Semi Inc. The authors discuss how the company's processors achieve high performance while consuming very low power. According to the authors, these processors are decedents of the extremely power-efficient StrongArm processor developed by Dan Dobberphul. The dual-core PA6T-1628M system on chip is the first design in the PWRficient family of high performance that target server class performance with power consumption. Some very interesting nuggets about low-power design are provided.

The article offers information on the first licensable, clockless 32-bit processor core, the ARM99BHS. It describes the architecture of ARM996HS and discusses the advantages of the clockless design methodology, including lower power consumption and decreased noise generation. According to the authors, the ARM996HS core is particularly interesting because it is clockless or self-clocked even though it can be embedded in a variety of technologies. Developed through the tide design flow, ARM996HS consumes about one-third the power of comparable synchronous, clock-gated, ARM cores implementing the same instruction set architecture.

A number of recent studies have revealed that the Optical Transpose Interconnection Systems (or OTIS) are promising candidates for future high-performance parallel computers. In this paper, we present and evaluate two general methods for algorithm development on the OTIS. The proposed methods are general in the sense that no specific factor network or problem domain is assumed. The proposed methods allow efficient mapping of a wide class of algorithms into the OTIS. These methods are based on grids and pipelines as popular structures that support a vast body of parallel applications including linear algebra, divide-and-conquer type of algorithms, sorting, and FFT computation. Timing models for measuring the performance of the proposed methods are also provided. Through these models, the performance of various algorithms on the OTIS are evaluated and compared with their counterparts on conventional electronic interconnection systems. This study confirms the viability of the OTIS as an attractive alternative for large-scale parallel architectures. Finally, we show how the proposed methods can be used to design parallel algorithms for linear algebra on the OTIS. [ABSTRACT FROM AUTHOR]

This article discusses on several studies building on theories and research from several domains investigating how gender differences interact with software. Gender differences suggest that females process information and solve problems in different ways than males do. It investigates whether software design should take gender differences into account. It discusses gender human-computer interaction which refers to how software relates to gender differences. It focuses on how gender-neutral software works, not on gender-oriented content.

This article announces the coverage of the IEEE Computer Society's publications for 2007. The Computer Society publications will address breaking developments, broad trends, historical perspectives, and emerging issues in all aspects of the computing profession. It publishes 14 technical magazines that include topics on Internet computing, graphics, microprocessors, test, and distributed systems. It highlights emerging technologies that promise to reshape the computing landscape and key topics include nanotechnology, car-based computing, and synthetic biology.

Abstract: With the increasing availability of high-performance massively parallel computer systems, the prevalence of sophisticated scientific simulation has grown rapidly. The complexity of the scientific models being simulated has also evolved, leading to a variety of coupled multi-physics simulation codes. Such cooperating parallel programs require fundamentally new interaction capabilities, to efficiently exchange parallel data structures and collectively invoke methods across programs. So-called “” research, as part of the common component architecture (CCA) effort, addresses these special and challenging needs, to provide generalized interfaces and tools that support flexible parallel data redistribution and parallel remote method invocation. Using this technology, distinct simulation codes with disparate distributed data decompositions can work together to achieve greater scientific discoveries. [Copyright &y& Elsevier]

The article focuses on the use of computer simulation technology, the technology of computer games, which caught the public attention in the U.S. Chess-playing computers captured the attention of early computer researchers compared with the computer simulation. As more programmers became skilled at writing games with simulation tools, they explore computer games, fantasy worlds. The computer game industry has used simulation technology to create a host of artificial and imaginary worlds. Therefore, people get their first exposure to computers through video games. INSET: IEEE Annals of the History of Computing.

Businesses reshape the territorial configuration of economic activity by creating new forms of organization as part of the innovation process. Focusing on the case of Dell Computer, this article builds an argument about the geographic development of economies that is structured around four elements: (1) the firm, (2) the innovation process occurring within the firm, (3) the business organization of the firm, and (4) the territory in which the firm operates and extracts profit. In tracing this route from the enterprise to territory, this article draws upon the notion of "communications revolutions" as a catalyst for the innovative impulse of firms. In adapting to communications revolutions, firms, such as Dell, emerge as innovators by learning to recalibrate the time increments that are expended during the steps of making and marketing products, thereby shifting competition from the product to the processes of capitalist circulation. This recalibration of time results in the creation of process-driven routines for making profit and a transformation in the organizational arrangements through which firms implement such routines. As firms reinvent forms of organization to implement these time-based innovative routines, they alter the linkages between adjacent steps in their profit-making activity. By reorganizing these linkages and changing the nature of business organization, innovative firms reconfigure the territory in which they operate and accumulate. This reconfiguration of territory, however, is not the mechanical result of efficiency criteria. Firms use power over other firms to redeploy the location of activity in their production networks in an effort to achieve time economies and innovative efficiencies. [ABSTRACT FROM AUTHOR]

The article presents information on multipass pipelining, a microarchitectural model that provides an alternative to out-of-order execution for tolerating memory access latencies. In order to achieve high-performance levels microprocessors exploit instruction-level parallelism and tolerate memory-access latencies. Unlike microprocessors, out-of-order microprocessors do this by dynamically scheduling instruction execution, but require power-hungry hardware structures. Multipass pipelining uses two or more passes of preexecution or execution to achieve performance efficacy. It assumes compile-time scheduling for lower-power and lower-complexity exploitation of instruction-level parallelism, and unlike traditional in-order processors, allows persistent advance execution of instructions beyond those that are interlocked on a cache miss. The pipeline persistently executes instructions that are ready and skips over those that are not ready. Multipass pipelining enhances the in-order runahead and lets in-order processors perform useful processing instead of stalling while an instruction waits on a data cache miss.

The article presents information on a new memory scheduling approach that makes decisions based on the history of recently scheduled operations. Recently memory bandwidth has become an increasingly important resource. This is because the gap between processor and memory speeds has led to aggressive use of techniques such as prefetching, speculation and multithreading, which consume bandwidth to hide or reduce memory latency. This demand has been further added by the architectural trends toward multicore chips and application trends toward multimedia workloads. Even though modern DRAMs have hierarchical structures that allow multiple memory commands to concurrently access different substructures DRAMs with 5D structure and many different types of internal latencies make more sophisticated memory scheduling schemes necessary. A history-based scheduler selects the next memory command from the history of recently scheduled memory commands and the set of available commands from the reorder queues.

The article presents information on how runahead execution significantly increases a high-performance processor's ability to tolerate long main-memory latencies. High-performance processors today face main-memory latencies on the order of hundreds of processor clock cycles. Runahead execution improves a processor's performance by speculatively pre-executing the application program while the processor services a long-latency (L2) data cache miss. It lets a processor execute instructions that it otherwise couldn't execute under an L2 cache miss. Runahead execution provides the memory-level parallelism benefits of a large instruction window without requiring the large, complex, slow, and power-hungry structures. It increases the processor's ability to tolerate long main-memory latencies because it has modest hardware cost and doesn't significantly increase processor complexity. However, runahead execution significantly increases a processor's dynamic energy consumption by increasing the number of speculatively processed instructions.

The article presents information on new load-store processing algorithms for latency tolerant architectures. Memory latency tolerant architectures can achieve high performance by supporting thousands of in-flight instructions. Even though these architectures can achieve high performance without scaling cycle-critical processor resources they require large load and store queues to track all loads and stores executed while a long latency miss is pending. These architectures can effectively tolerate increasing memory latencies by executing thousands of useful miss-independent instructions in parallel with the pending miss. Latency-tolerant processors achieve large instruction windows by ensuring that instructions depending on a long-latency miss do not block cycle-critical processor resources, which then become available for subsequent miss-independent instructions to execute and complete. These instructions can execute and speculatively retire and freeing up their resources in the process.

The architecture and design of the IBM eServer™ BladeCenter® system make it an ideal platform for many information technology (IT) solutions. Its high availability, modularity, flexible infrastructure integration, and on demand configuration options have prompted developers within IBM and in end-user IT organizations to create solutions tailored to a particular industry or function. This paper describes the BladeCenter system in the application of several of these solutions--their target enterprises, end-users, and key benefits. High-performance and scientific clusters, branch-office-in-a-box, financial services, and hostedclient solutions are reviewed. [ABSTRACT FROM AUTHOR]

Virtualization technologies encompass a variety of mechanisms and techniques used to address computer system problems such as security, performance, and reliability by decoupling the architecture and user perceived behavior of hardware and software resources from their physical implementation. This article focuses on virtual machine monitors (VMMs), a key component of virtual machines that provides a layer between software environments and physical hardware that is programmable. A discussion is presented on the various perspectives of VMMs.

Good performance monitoring is the basis of modern performance analysis tools for application optimization. We are providing a variety of such performance analysis tools for the new Blue Gene®/L supercomputer. Those tools can be divided into two categories: single-node performance tools and multinode performance tools. From a single-node perspective, we provide standard interfaces and libraries, such as PAPI and libHPM, that provide access to the hardware performance counters for applications running on the Blue Gene/L compute nodes. From a multinode perspective, we focus on tools that analyze Message Passing Interface (MPI) behavior. Those tools work by first collecting message-passing trace data when a program runs. The trace data is then used by graphical interface tools that analyze the behavior of applications. Using the current prototype tools, we demonstrate their usefulness and applicability with case studies of application optimization. [ABSTRACT FROM AUTHOR]

This article analyzes a novel framework for estimating power in embedded computer systems. Among the many metrics used to characterize the quality of an embedded system-on-chip design, power consumption has emerged as the most important. This is largely due to the proliferation of mobile battery-powered computer devices. A technique was developed that derives power figures from the execution of high-level models. This technique makes it possible to access embedded computer system designs much earlier in the design cycle, contributing to sounder decisions throughout the entire development process and leading to a faster execution time. To validate the method, it was applied to a peripheral core and compared the results with those using a gate-level approach.

Focuses on the projections made by researchers in 1997 concerning the direction of billion-transistor microprocessor architectures. Categorization of constraints that would affect architectures over the next decade; Review of visions of what billion-transistor architectures would be in the future; Emergence of constraints and trends since 1997 which affect the move toward balanced and scalable billion-transistor architectures.