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A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components. [ABSTRACT FROM AUTHOR]

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]

Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phase-locked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from $95.3\;\mu {{\rm{V}}_{{\rm{RMS}}}}$ down to $14.8\;\mu {{\rm{V}}_{{\rm{RMS}}}} . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40\;\mu \rmA . It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1–3.3 V. Fabricated in a 0.25\;\mu \rmm CMOS process, the LDO core occupies an area of 0.18 mm2. [ABSTRACT FROM AUTHOR]

Efficient current, voltage, and power sensing are critical blocks for power management, switching regulators, maximum power point tracking (MPPT) circuit, and motor control. This paper presents a standard CMOS and low-power current-to-digital converter (IDC) that senses the current flowing at high-voltage nodes. The proposed sensor uses a CMOS-switched capacitor circuit to sense a dc–dc converter output current and gives digital output without an analog-to-digital converter (ADC), or the need for high-voltage technologies. Compared to the resistor-based current-sensing methods that require current-to-voltage circuit, gain block, and an ADC converter, the proposed sensor is a low-power integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 5 V, 0.7 μm, and three metal CMOS technology and occupied less than 10% area (1 mm2 area) compared to other sensors. It consumes 18 mW that is less than 40% power consumed by other sensors, and its current measurement error is below 0.4%. The proposed IDC circuit has been characterized as standalone and with a boost dc–dc regulator and MPPT for photovoltaic systems. [ABSTRACT FROM AUTHOR]

An all-digital sliding-mode (ADSM) controlled dc-dc converter, utilizing single-bit oversampled frequency domain digitizers in its feedback path is proposed. Sliding-mode control provides several benefits over the traditional PID control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. However, analog implementations of sliding-mode control require several amplifiers in the controller and suffer from process, voltage, and temperature variations. In the proposed approach, the sliding-mode controller (SMC) is implemented digitally; utilizing a first order single-bit ΣΔ frequency to digital converter (ΣΔFDC)-based feedback and reference digitizing ADCs, running at 32-MHz sampling rate. The ADSM regulator achieves 1% settling time in less than 5 μs for a load variation of 600 mA. The SMC uses a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady-state error (or dc offset), and band limits the switching frequency, which are the two common problems associated with SMCs. The IC is designed and fabricated on a 0.35-μm CMOS process occupying an active area of 2.72 mm2. [ABSTRACT FROM AUTHOR]