11 results on '"Bagherzadeh, Nader"'
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2. First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip.
- Author
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Charif, Amir, Coelho, Alexandre, Ebrahimi, Masoumeh, Bagherzadeh, Nader, and Zergainoh, Nacer-Eddine
- Subjects
ADAPTIVE routing (Computer network management) ,THROUGH-silicon via ,MULTIPROCESSORS ,COST effectiveness ,COMPUTER algorithms - Abstract
3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shown to dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. A comprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects to existing solutions. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
3. LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification.
- Author
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Salamat, Ronak, Khayambashi, Misagh, Ebrahimi, Masoumeh, and Bagherzadeh, Nader
- Subjects
ROUTING algorithms ,QUEUING theory ,NETWORKS on a chip ,MULTICORE processors ,ROUTING (Computer network management) - Abstract
2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
4. A Compositional Approach for Verifying Protocols Running on On-Chip Networks.
- Author
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Verbeek, Freek, Yaghini, Pooria M., Eghbal, Ashkan, and Bagherzadeh, Nader
- Subjects
ROUTING (Computer network management) ,INTEGRATED circuits ,MULTIPROCESSORS ,COMPUTER architecture ,INTERNET traffic - Abstract
In modern many-core architectures, advanced on-chip networks provide the means of communication for the cores. This greatly complicates the design and verification of the cache coherence protocols deployed by those cores. A common approach to deal with this complexity is to decompose the whole system into the protocol and the network. This decomposition is, however, not always possible. For example, unexpected deadlocks can emerge when a deadlock-free protocol and a deadlock-free network are combined. This paper proposes a compositional methodology: prove properties over a network, prove properties over a protocol, and infer properties over the system as a whole. Our methodology is based on theorems that show that such decomposition is possible by having sufficiently large local buffers at the cores. We apply this methodology to verify several protocols such as MI, MSI, MESI and MEUSI running on top of advanced interconnects with adaptive routing. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
5. AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs.
- Author
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Ghaderi, Zana, Alqahtani, Ayed, and Bagherzadeh, Nader
- Subjects
ADAPTIVE routing (Computer network management) ,NETWORKS on a chip ,COMPUTER algorithms ,ONLINE monitoring systems ,THREE-dimensional imaging - Abstract
The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve area, performance, power, and scalability of many-core systems. However, reliability issue as a perpetual challenge in advanced silicon technology imperils it. Aging is an emerging reliability concern, which degrades the system's performance and causes timing failure eventually. Bias-Temperature-Instability (BTI) and Hot-Carrier-Injection (HCI) are the dominant aging mechanisms, which escalate in high temperature and stress (i.e., usage). In addition to the intra-layer temperature variations, 3D NoCs experience inter-layer temperature variations, which demand necessary investigations for aging as compared to 2D NoC. In this paper, we propose AROMa, an aging-aware deadlock-free adaptive routing algorithm integrated with a novel online aging monitoring system for 3D NoCs. The monitoring system in AROMa exploits Distributed-Centralized-Aging-Table (D-CAT) to obtain routers’ aging rates for each layer of 3D NoCs periodically. Consequently, AROMa swaps between different k-best source-destination shortest paths periodically to avoid highly aged routers, force them in recovery phase of BTI, and accordingly balance aging in the network. We prove that AROMa is deadlock free. Our extensive experimental analysis using gem5 full system mode for PARSEC and SPLASH-2 benchmark suites concludes that AROMa outperforms state-of-the-art works while improving age imbalance by 70 percent and maximum age by 35 percent in 3D NoC with negligible overheads. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
6. A General Fault-Tolerant Minimal Routing for Mesh Architectures.
- Author
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Zhao, Hongzhi, Bagherzadeh, Nader, and Wu, Jie
- Subjects
- *
FAULT-tolerant computing , *ROUTING (Computer network management) , *COMPUTER architecture , *COMPUTATIONAL complexity , *NETWORKS on a chip - Abstract
Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault-tolerant minimal path should also be routed around. How to label such non-faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address it very well. We propose a path-counter method. It can label every node that are helpless to make up of a fault-tolerant minimal path with low time complexity. By counter the number of fault-tolerant minimal paths, it can: support arbitrary fault distribution, check the existence of fault-tolerant minimal paths, not sacrifice any available fault-tolerant minimal paths. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
7. A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs.
- Author
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Salamat, Ronak, Khayambashi, Misagh, Ebrahimi, Masoumeh, and Bagherzadeh, Nader
- Subjects
NETWORKS on a chip ,COMPUTER architecture ,ADAPTIVE routing (Computer network management) ,ROUTING algorithms ,FAULT tolerance (Engineering) - Abstract
3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$
dimension. [ABSTRACT FROM AUTHOR]- Published
- 2016
- Full Text
- View/download PDF
8. Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation.
- Author
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Agyeman, Michael Opoku, Ahmadinia, Ali, and Bagherzadeh, Nader
- Subjects
MULTIPROCESSORS ,CENTRAL processing units ,SEMICONDUCTOR wafers ,NETWORK routers ,COMPUTER networks - Abstract
Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
9. Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip.
- Author
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Wang, Chifeng and Bagherzadeh, Nader
- Abstract
This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
10. LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC.
- Author
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Azampanah, Sanaz, Khademzadeh, Ahmad, Bagherzadeh, Nader, Janidarmian, Majid, and Shojaee, Reza
- Abstract
NoC performance largely depends on the underlying deadlock-free and efficient routing algorithm. Selection strategies play a pivotal role in the effectiveness of the routing algorithm by selecting the final output channel when there is more than one possible output link returned by an adaptive routing. In this paper a novel selection strategy, LATEX, is proposed that can be used with any adaptive routing algorithm for specified applications. The objective of the proposed selection strategy is to efficiently balance traffic load and reach better performance results. Performance evaluation is carried out by using a flit-accurate simulator under two real traffic scenarios. Result experiments show that the proposed selection strategy applied to several routing algorithms significantly improves average delay, max delay and power consumption. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
11. Design and Analysis of a Mesh-based Wireless Network-on-Chip.
- Author
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Hu, Wen-Hsiang, Wang, Chifeng, and Bagherzadeh, Nader
- Abstract
Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements. To solve these limitations, we employed on-chip wireless communication as express links for transferring data so that transfer latency can be reduced. A hybrid NoC architecture utilizing both wired and wireless communication approaches is proposed in this paper. We also devised a deadlock free routing algorithm that is able to make efficient use of the incorporated wireless links. Moreover, simulated annealing optimization techniques were applied to find optimal locations for wireless routers. Cycle-accurate simulation results showed a significant improvement in transfer latency. Area and power consumption analysis demonstrates the feasibility of our proposed NoC architecture. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
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