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An isolated four channel dc/dc converter with zero voltage switching is proposed as the front-end of multiple inverter structures to integrate renewable and other low voltage energy sources to micro grids. The interleaving technique is adopted to connect each module of proposed converter to a common dc source. This dc source can be a fuel cell stack, PV panels, battery, or any other low voltage dc source. All four channels are interleaved and a phase shift of $90^{\circ }$ is provided between the gate signals of each channels, which reduces the input current ripple. The output port of the proposed converter provide four isolated and regulated dc voltages. These isolated dc sources can be connected in series or parallel or series-parallel manner to obtain required dc-link voltage of various inverter structure. Issues like capacitor voltage balancing of diode clamped multilevel inverters can overcome through the proposed converter. By incorporating a coupled inductor for isolation and energy storage along with voltage multiplier circuit, the proposed converter can achieve higher voltage step up with lower turns ratio and lower voltage stress at moderate duty ratio. Hence, mosfets of low voltage rating (low $R_{DS}(\text{ON})$ ) can be utilized to reduce conduction loss. A 2 kW prototype of the proposed interleaved dc/dc converter is developed and tested with diode clamped three-level inverter, five-level inverter, and three-phase two-level inverter to verify the design. [ABSTRACT FROM AUTHOR]

The use of the dynamic voltage restorer (DVR) is preferred for the mitigation of voltage quality disturbances. In this paper, the real-time application of a 5-level transistor clamped H-bridge inverter for the single-phase DVR to realize the voltage sag mitigation is discussed. The controller is realized by comparing a sensitive load voltage with a reference voltage generated by the unit vector template method. MATLAB Simulink software is used to test the ability of the developed DVR by employing the in-phase and pre-sag compensation techniques. In addition, an experimental evaluation is performed in real time to observe the compensation capability of a 5-level transistor clamped H-bridge DVR. The design details of developed DVR are discussed, a prototype of DVR is also built in the laboratory. For verification of the capability of proposed DVR topology for voltage sag mitigation, experimental findings are presented. [ABSTRACT FROM AUTHOR]

This paper presents simplified techniques for the space vector modulation (SVM) of any n-level multilevel inverter. Three techniques have been presented to simplify the identification of the nearest three vectors to the reference vector. The first two techniques are based on resolving the multilevel inverter space vector diagram into appropriate two-level hexagons. This results in simplification of the multilevel SVM problem into a two-level SVM problem. The third technique is an algorithm-based technique which makes use of a 60°-spaced gh coordinate system to perform the SVM of a multilevel inverter. Switching sequence design for all the three techniques is presented with the aim of minimization of the device switching frequency. Simulation and experimental results have been provided to verify the feasibility of the proposed techniques. Simulation results are provided for up to 21-level cascaded H-bridge (CHB) inverters, while the experimental verification is done on a five-level laboratory prototype. Although only the CHB inverter is considered in this study, the proposed techniques are perfectly general and can be applied to all types of multilevel inverters, and are extendable to any number of levels. [ABSTRACT FROM AUTHOR]

In this paper, a single phase modified switched-diode topology for both symmetrical and asymmetrical cascaded multilevel inverters is presented. It consists of a Modified Switched-Diode Unit (MSDU) and a Twin Source Two Switch Unit (TSTSU) to produce distinct positive voltage levels according to the operating modes. An additional H-bridge synthesizes a voltage waveform, where the voltage levels of either polarity have less Total Harmonic Distortion (THD). Higher-level inverters can be built by cascading MSDUs. A comparative analysis is done with other topologies. The proposed topology results in reductions in the number of power switches, losses, installation area, voltage stress and converter cost. The Nearest Level Control (NLC) technique is employed to generate the gating signals for the power switches. To verify the performance of the proposed structure, simulation results are carried out by a PSIM under both steady state and dynamic conditions. Experimental results are presented to validate the simulation results. [ABSTRACT FROM AUTHOR]

A simplified space vector modulation (SVM) technique is proposed for the seven-level cascaded H-bridge (CHB) inverter. It is based on decomposing the seven-level space vector hexagon into a number of two-level space vector hexagons. The presented technique significantly reduces the calculation time and efforts involved in the SVM of a seven-level inverter; without any loss in the output voltage magnitude or increase in the total harmonic distortion content. A further simplified technique is also presented in this study, which significantly reduces the complexity and effort involved in the seven-level SVM. Simulation results for the seven-level CHB inverter using the proposed techniques are presented. The results are compared with results using sinusoidal pulse-width modulation (PWM) and third harmonic injection PWM to prove the validity of the proposed techniques. The proposed technique is perfectly general and can be applied to all types of multilevel inverters and extended to higher level inverters. [ABSTRACT FROM AUTHOR]

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit. [ABSTRACT FROM AUTHOR]