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We give an infinite family of maximum rank distance (MRD) codes, which covers properly the largest known linear MRD code family. Our family contains infinite families of non-linear MRD codes, which are the first non-linear examples for most of the parameters. We also give explicit examples and a table that demonstrates the proportion of linear and non-linear families for some small parameters. [ABSTRACT FROM PUBLISHER]

In this paper, list decoding of crisscross errors in arrays over finite fields is considered. For this purpose, the so-called cover metric is used, where the cover of a matrix is a set of rows and columns which contains all non-zero elements of the matrix. A Johnson-like upper bound on the maximum list size in the cover metric is derived, showing that the list of codewords has polynomial size up to a certain radius. Furthermore, a simple list decoding algorithm for a known optimal code construction is presented, which decodes errors in the cover metric up to our upper bound. These results reveal significant differences between the cover metric and the rank metric and show that the cover metric is more suitable for correcting crisscross errors. [ABSTRACT FROM PUBLISHER]

We consider codes over fixed alphabets against worst case symbol deletions. For any fixed k \ge 2 , we construct a family of codes over alphabet of size k with positive rate, which allow efficient recovery from a worst case deletion fraction approaching 1-(2/(k+\sqrt k)) . In particular, for binary codes, we are able to recover a fraction of deletions approaching 1/(\sqrt 2 +1)=\sqrt 2-1 \approx 0.414 . Previously, even non-constructively, the largest deletion fraction known to be correctable with positive rate was 1-\Theta (1/\sqrt k) , and around 0.17 for the binary case. Our result pins down the largest fraction of correctable deletions for $k$ -ary codes as 1-\Theta (1/k)$ , since 1-1/k$ is an upper bound even for the simpler model of erasures where the locations of the missing symbols are known. Closing the gap between and 1/2 for the limit of worst case deletions correctable by binary codes remains a tantalizing open question. [ABSTRACT FROM PUBLISHER]

We study error correction codes for multimedia streaming applications where a stream of source packets must be transmitted in real-time, with in-order decoding, and strict delay constraints. In our setup, the encoder observes a stream of source packets in a sequential fashion, and $M$ channel packets must be transmitted between the arrival of successive source packets. Each channel packet can depend on all the source packets observed up to and including that time, but not on any future source packets. The decoder must reconstruct the source stream with a delay of $T$ packets. We consider a class of packet erasure channels with burst and isolated erasures, where the erasure patterns are locally constrained. Our proposed model provides a tractable approximation to statistical models, such as the Gilbert–Elliott channel, for capacity analysis. When $M=1$ , i.e., when the source-packet arrival and channel-packet transmission rates are equal, we establish upper and lower bounds on the capacity, that are within one unit of the decoding delay $T$ . We also establish necessary and sufficient conditions on the column distance and column span of a convolutional code to be feasible, and in turn establish a fundamental tradeoff between these. Our proposed codes—maximum distance and span codes—achieve a near-optimal tradeoff between the column distance and column span, and involve a layered construction. When $M>1$ , we establish the capacity for the burst-erasure channel and an achievable rate in the general case. Extensive numerical simulations over Gilbert–Elliott and Fritchman channel models suggest that our codes also achieve significant gains in the residual loss probability over statistical channel models. [ABSTRACT FROM PUBLISHER]

Error-correcting output coding (ECOC) is one of the most widely used strategies for dealing with multi-class problems by decomposing the original multi-class problem into a series of binary sub-problems. In traditional ECOC-based methods, binary classifiers corresponding to those sub-problems are usually trained separately without considering the relationships among these classifiers. However, as these classifiers are established on the same training data, there may be some inherent relationships among them. Exploiting such relationships can potentially improve the generalization performances of individual classifiers, and, thus, boost ECOC learning algorithms. In this paper, we explore to mine and utilize such relationship through a joint classifier learning method, by integrating the training of binary classifiers and the learning of the relationship among them into a unified objective function. We also develop an efficient alternating optimization algorithm to solve the objective function. To evaluate the proposed method, we perform a series of experiments on eleven datasets from the UCI machine learning repository as well as two datasets from real-world image recognition tasks. The experimental results demonstrate the efficacy of the proposed method, compared with state-of-the-art methods for ECOC-based multi-class classification. [ABSTRACT FROM PUBLISHER]

The design and implementation of an error detection and correction scheme in a MODBUS-RTU network based on the REED-SOLOMON code is presented. The transmission of the parity bits is made respecting the parameters of the MODBUS protocol, so the bus can be used by common devices without the error detection/correction scheme. The error detection–correction is performed by means of specialized repeating devices in the receiver and transmitter. This method respects the parameters of the MODBUS-RTU protocol, so the bus enhanced with retransmitter devices can be used along with common devices. Finally, the implementation of an experimental network is described and the practical results obtained are given. [ABSTRACT FROM AUTHOR]

Resistive memories are affected by significant error rates tied to structural relaxation and wear out of the resistive memory devices. A way to reduce the need for strong error-correcting codes (ECCs) is to improve error correction based on the weak bits, i.e., potentially faulty bits, identified in sensed memory words. Here, it is formally proven that conventional ECC decoders reinforced with weak-bit-flipping may achieve similar error correction capability as theoretical generalized-minimum-distance decoders. It is shown that weak-bit-flipping may reduce the uncorrectable bit error rate (UBER) by orders of magnitude when applied in conjunction with single-error-correcting and double-error-detecting (SEC-DED) or double-error-correcting and triple-error-detecting (DEC-TED) codes. In particular, weak-bit-information extracted from a 2T2R memory and used to reinforce a DEC-TED code with a conventional decoder may enable an UBER that is one order of magnitude better than the UBER achieved with a triple-error-correcting (TEC) code and a conventional decoder. • A conventional errors-only decoder with weak-bit-flipping can outperform an erasures-and-errors decoder • A conventional errors-only decoder with weak-bit-flipping can outperform a generalized-minimum-distance decoder • The impact of weak-bit-flipping on error correction is estimated starting from resistance state distributions • The formalism used to estimate the efficiency of weak-bit-flipping is independent of the weak-bit-identification scheme [ABSTRACT FROM AUTHOR]

We propose binary discrete parametric channel models for multi-level cell (MLC) flash memories that provide accurate error-correcting code (ECC) performance estimation by modeling the empirically observed error characteristics under program/erase cycling stress. Through a detailed empirical error characterization of 1X-nm and 2Y-nm MLC flash memory chips from two different vendors, we observe and characterize the overdispersion phenomenon in the number of bit errors per ECC frame. A well-studied channel model, such as the binary asymmetric channel model, is unable to provide accurate ECC performance estimation. Hence, we propose a channel model based on the beta-binomial probability distribution [2-beta-binomial (2-BBM) channel model], which is a good fit for the overdispersed empirical error characteristics, and show through statistical tests and simulation results for BCH, low density parity check, and polar codes, that the 2-BBM channel model provides accurate ECC performance estimation in MLC flash memories. [ABSTRACT FROM AUTHOR]

Error correction code (ECC) and built-in self-repair (BISR) techniques by using redundancies have been widely used for improving the yield and reliability of embedded memories. The target faults of these two schemes are soft errors and permanent (hard) faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability, since some of the ECC protection capability is used for repairing single hard faults. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique, which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-ON test and repair stage. However, techniques are proposed to maintain the original reliability during the online test and repair stage. We also propose the corresponding hardware architecture for the EBISR scheme. A simulator is implemented to evaluate the hardware overhead (HO), repair rate, reliability, and performance penalty. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible HO and performance penalty. [ABSTRACT FROM PUBLISHER]

Two families of new asymmetric quantum codes are constructed in this paper. The first family is the asymmetric quantum codes with length $$n=q^{m}-1$$ over $$F_{q}$$ , where $$q\ge 5$$ is a prime power. The second one is the asymmetric quantum codes with length $$n=3^{m}-1$$ . These asymmetric quantum codes are derived from the CSS construction and pairs of nested BCH codes. Moreover, let the defining set $$T_{1}=T_{2}^{-q}$$ , then the real Z-distance of our asymmetric quantum codes are much larger than $$\delta _\mathrm{max}+1$$ , where $$\delta _\mathrm{max}$$ is the maximal designed distance of dual-containing narrow-sense BCH code, and the parameters presented here have better than the ones available in the literature. [ABSTRACT FROM AUTHOR]

This paper reviews the developments in saving and investment in Ethiopia over the past fifteen years. An attempt was made to establish factors that have been most influential to these developments and to determine their respective impacts. The paper employs recent techniques in time series econometrics, namely cointegration (CI) analysis and error correction modelling (ECM) to determine the long and short-term impacts of determinants of saving and investment in Ethiopia. The results reveal that private saving in Ethiopia is only significantly influenced by real income, while bank deposit rates exerts little, if any, influences. Further, factors such as real lending and deposit rates, inflation, and real income, public saving, dependency ratio and government investments are important determinants of investments in Ethiopia. It is also revealed that Ethiopia's savings level has been not satisfactory by international standards, but the investment performance has been flourishing in recent period, resulting in a faster economic growth than expected. While the poor performance of saving is attributable to various factors, low real deposit rate and high government deficit are the major problems that must be addressed as a priority for Ethiopia to attain higher growth targets in the future. [ABSTRACT FROM AUTHOR]

We present the first model of optimal voting under adversarial noise. From this viewpoint, voting rules are seen as error-correcting codes: their goal is to correct errors in the input rankings and recover a ranking that is close to the ground truth. We derive worst-case bounds on the relation between the average accuracy of the input votes, and the accuracy of the output ranking. Empirical results from real data show that our approach produces significantly more accurate rankings than alternative approaches. [ABSTRACT FROM AUTHOR]

In pebbling problems, pebbles are placed on the vertices of a graph. A pebbling move consists of removing two pebbles from one vertex, throwing one away, and moving the other pebble to an adjacent vertex. We say a distribution D is solvable if starting from D , we can move a pebble to any vertex by a sequence of pebbling moves. The optimal pebbling number of a graph G is the smallest number of pebbles in a solvable distribution on G . It is known that every solvable distribution on the n -dimensional hypercube Q n contains at least ( 4 3 ) n pebbles. Fu, Huang, and Shiue, building on the work of Moews, used probabilistic methods to show that there are solvable distributions where the number of pebbles is in O ( ( 4 3 ) n n 3 2 ) , but hitherto, the number of pebbles in the best constructed distributions was in O ( 1.37 7 n ) . We use error-correcting codes to construct solvable distributions of pebbles on Q n in which the number of pebbles is in O ( 1.3 4 n ) . [ABSTRACT FROM AUTHOR]

While traditionally considered for non-stationary and cointegrated data, DeBoef and Keele suggest applying a General Error Correction Model (GECM) to stationary data with or without cointegration. The GECM has since become extremely popular in political science but practitioners have confused essential points. For one, the model is treated as perfectly flexible when, in fact, the opposite is true. Time series of various orders of integration-stationary, non-stationary, explosive, near- and fractionally integrated-should not be analyzed together but researchers consistently make this mistake. That is, without equation balance the model is misspecified and hypothesis tests and long-run-multipliers are unreliable. Another problem is that the error correction term's sampling distribution moves dramatically depending upon the order of integration, sample size, number of covariates, and the boundedness of Yt. This means that practitioners are likely to overstate evidence of error correction, especially when using a traditional t-test. We evaluate common GECM practices with six types of data, 746 simulations, and five paper replications. [ABSTRACT FROM AUTHOR]

The code design of non-binary low-density parity-check codes for the erasure channel, under maximum a posteriori decoding, is addressed. In particular, a partially structured ensemble of codes, characterized by a careful control of the amount and of the connectivity of the variable nodes of small degrees, is proposed. The identified ensemble of codes is analyzed in terms of asymptotic thresholds and weight distribution and it is shown that codes from the ensemble provide a remarkable trade-off between waterfall performance, error floor, and decoding complexity. As an example, the performance curve of a short (256,128) code on the memoryless 16-ary erasure channel tightly approaches the Singleton bound at least down to a codeword error rate of 10^-9, at low decoding complexity. [ABSTRACT FROM AUTHOR]

Polar codes, as the first provable capacity-achieving error-correcting codes, have received much attention in recent years. However, the decoding performance of polar codes with traditional successive-cancellation (SC) algorithm cannot match that of the low-density parity-check or Turbo codes. Because SC list (SCL) decoding algorithm can significantly improve the error-correcting performance of polar codes, design of SCL decoders is important for polar codes to be deployed in practical applications. However, because the prior latency reduction approaches for SC decoders are not applicable for SCL decoders, these list decoders suffer from the long-latency bottleneck. In this paper, we propose a multibit-decision approach that can significantly reduce latency of SCL decoders. First, we present a reformulated SCL algorithm that can perform intermediate decoding of 2 b together. The proposed approach, referred as 2-bit reformulated SCL (2b-rSCL) algorithm, can reduce the latency of SCL decoder from ( 3n-2 ) to ( 2n-2 ) clock cycles without any performance loss. Then, we extend the idea of 2-b-decision to general case, and propose a general decoding scheme that can perform intermediate decoding of any 2^K bits simultaneously. This general approach, referred as \textit 2^K -bit reformulated SCL ( 2^K b-rSCL) algorithm, can reduce the overall decoding latency to as short as n/2^K-2-2 cycles. Furthermore, on the basis of the proposed algorithms, very large-scale integration architectures for 2b-rSCL and 4b-rSCL decoders are synthesized. Compared with a prior SCL decoder, the proposed (1024, 512) 2b-rSCL and 4b-rSCL decoders can achieve 21% and 60% reduction in latency, 1.66 and 2.77 times increase in coded throughput with list size 2, and 2.11 and 3.23 times increase in coded throughput with list size 4, respectively. [ABSTRACT FROM PUBLISHER]

This brief lays out cyclic redundancy check-based encoding scheme and presents an efficient implementation of the encoding algorithm in field programmable gate array (FPGA) prototype for both the binary Golay code ( G\mathrm {\mathbf {23}} ) and extended binary Golay code ( G\mathrm {\mathbf {24}} ). High speed with low-latency architecture has been designed and implemented in Virtex-4 FPGA for Golay encoder without incorporating linear feedback shift register. This brief also presents an optimized and low-complexity decoding architecture for extended binary Golay code (24, 12, 8) based on an incomplete maximum likelihood decoding scheme. The proposed architecture for decoder occupies less area and has lower latency than some of the recent work published in this area. The encoder module runs at 238.575 MHz, while the proposed architecture for decoder has an operating clock frequency of 195.028 MHz. The proposed hardware modules may be a good candidate for forward error correction in communication link, which demands a high-speed system. [ABSTRACT FROM AUTHOR]

Improved lower and upper bounds on the size and the rate of grain-correcting codes are presented. The lower bound is Gilbert–Varshamov-like combined with a construction by Gabrys et al., and it improves on the previously best known lower bounds on the asymptotic rate of \lceil \tau n \rceil -grain-correcting codes of length n on the interval [0,0.0668] . One of the two newly presented upper bounds improves on the best known upper bounds on the asymptotic rate of \lceil \tau n \rceil -grain-correcting codes of length n on the interval \tau \in (0,{1}/{8}] and meets the lower bound of {1}/{2} for \tau \geq 1/8 . Moreover, in a nonasymptotic regime, both upper bounds improve on the previously best known results on the largest size of t -grain-correcting codes of length $n$ , for certain values of n$ and t$ . Constructions of 1-grain-correcting codes based on a partitioning technique are presented for lengths up to 18. Finally, a lower bound of on the minimum redundancy of $\infty $ -grain-detecting codes of length $n$ is presented. [ABSTRACT FROM PUBLISHER]

Random network coding recently attracts attention as a technique to disseminate information in a network. This paper considers a noncoherent multishot network, where the unknown and time-variant network is used several times. In order to create dependence between the different shots, particular convolutional codes in rank metric are used. These codes are so-called (partial) unit memory ((P)UM) codes, i.e., convolutional codes with memory one. First, distance measures for convolutional codes in rank metric are shown and two constructions of (P)UM codes in rank metric based on the generator matrices of maximum rank distance codes are presented. Second, an efficient error-erasure decoding algorithm for these codes is presented. Its guaranteed decoding radius is derived and its complexity is bounded. Finally, it is shown how to apply these codes for error correction in random linear and affine network coding. [ABSTRACT FROM AUTHOR]

Incorporating information security and error correction in network coding, which has various applications in communication theory, for example, secret key sharing through a network, is of special interest and has been widely studied. To make a more intensive analysis of secure error-correcting network codes, we investigate how to secure k source symbols transmission in a multicast network against an adversary that can obtain k1 source symbols as side information, eavesdrop µ channels and contaminate d channels. We introduce relative network generalised Hamming weight (RNGHW) with network error correction (NEC), or briefly NEC-RNGHW, to measure the equivocation to the adversary. Network generalised singleton bound on NEC-RNGHW is obtained and code constructions achieving the bound are provided. By these constructions, the maximum rate of a secure linear multicast is n - 2d - &#µ; - k1, where n is the minimum value of the maxflows from a source node to sink nodes. We also characterise the equivocation by the relative profiles of a linear code and a subcode, and tighten the singleton bound on equivocation by the generalised Griesmer bound on relative profiles. [ABSTRACT FROM AUTHOR]

Several bounds on the size of ( n + l , M , d , ( m , 0 ) ) q codes in attenuated space over finite fields are provided in this paper. Then, we prove that codes in attenuated space attain the Wang–Xing–Safavi-Naini bound if and only if they are certain Steiner structures. [ABSTRACT FROM AUTHOR]

We present new constructions of codes for asymmetric channels for both binary and nonbinary alphabets, based on methods of generalized code concatenation. For the binary asymmetric channel, our methods construct nonlinear single-error-correcting codes from ternary outer codes. We show that some of the Varshamov–Tenengol’ts–Constantin–Rao codes, a class of binary nonlinear codes for this channel, have a nice structure when viewed as ternary codes. In many cases, our ternary construction yields even better codes. For the nonbinary asymmetric channel, our methods construct linear codes for many lengths and distances which are superior to the linear codes of the same length capable of correcting the same number of symmetric errors. [ABSTRACT FROM AUTHOR]

Generalized balanced tournament packings (GBTPs) extend the concept of generalized balanced tournament designs introduced by Lamken and Vanstone (1989). In this paper, we establish the connection between GBTPs and a class of codes called equitable symbol weight codes (ESWCs). The latter were recently demonstrated to optimize the performance against narrowband noise in a general coded modulation scheme for power line communications. By constructing classes of GBTPs, we establish infinite families of optimal ESWCs with code lengths greater than alphabet size and whose narrowband noise error-correcting capability to code length ratios do not diminish to zero as the length grows. [ABSTRACT FROM AUTHOR]

This work presents a study of the complexity of the Blum-Kalai-Wasserman (BKW) algorithm when applied to the Learning with Errors (LWE) problem, by providing refined estimates for the data and computational effort requirements for solving concrete instances of the LWE problem. We apply this refined analysis to suggested parameters for various LWE-based cryptographic schemes from the literature and compare with alternative approaches based on lattice reduction. As a result, we provide new upper bounds for the concrete hardness of these LWE-based schemes. Rather surprisingly, it appears that BKW algorithm outperforms known estimates for lattice reduction algorithms starting in dimension $$n \approx 250$$ when LWE is reduced to SIS. However, this assumes access to an unbounded number of LWE samples. [ABSTRACT FROM AUTHOR]

Quantum synchronizable error-correcting codes are special quantum error-correcting codes that are designed to correct both the effect of quantum noise on qubits and misalignment in block synchronization. It is known that, in principle, such a code can be constructed through a combination of a classical linear code and its subcode if the two are both cyclic and dual-containing. However, finding such classical codes that lead to promising quantum synchronizable error-correcting codes is not a trivial task. In fact, although there are two families of classical codes that are proved to produce quantum synchronizable codes with good minimum distances and highest possible tolerance against misalignment, their code lengths have been restricted to primes and Mersenne numbers. In this paper, examining the incidence vectors of projective spaces over the finite fields of characteristic 2, we give quantum synchronizable codes from cyclic codes whose lengths are not primes or Mersenne numbers. These projective geometric codes achieve good performance in quantum error correction and possess the best possible ability to recover synchronization, thereby enriching the variety of good quantum synchronizable codes. We also extend the current knowledge of cyclic codes in classical coding theory by explicitly giving generator polynomials of the finite geometric codes and completely characterizing the minimum weight nonzero codewords. In addition to the codes based on projective spaces, we carry out a similar analysis on the well-known cyclic codes from Euclidean spaces that are known to be majority logic decodable and determine their exact minimum distances. [ABSTRACT FROM PUBLISHER]

ABSTRACT Consider a signed file that cannot be verified because of some fraction loss or noise, which might not affect the business of users. It would be desirable for the verifier to locate the damaged fractions so that the authenticity of other components of the file can be ensured. Thereafter, the verifier can decide whether or not to accept it. To address this issue, in this paper, we present a loss-tolerant authentication scheme, which allows the verifier to locate the damaged elements in the signed file stream. Our idea is to allow the signed file to be fragmented, and each fragment is appended a short authentication tag, which enables the verifier to find the modified fragments in the signed file and verify the signature even if some fragments are lost. The proposed scheme adopts a combination of Reed-Solomon error correction and erasure codes, aiming to allow verifiers to locate the modified fractions and thereafter reconstruct the signature when sufficient original fractions of the file are obtained. Our scheme offers many potential applications such as loss-tolerant transmission and storage. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

We propose a method for improving noise immunity in data transmission channels for telemetry information systems by providing double byte data error correction with minimal time delay. [ABSTRACT FROM AUTHOR]

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link. [ABSTRACT FROM AUTHOR]

A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. For a (40, 33) code, the proposed architecture reduces the latency and the hardware complexity by \sim32\% and 9%, respectively, compared with the most recent implementation. [ABSTRACT FROM AUTHOR]

Error correction codes (ECCs) are commonly used to protect memories from errors. As multibit errors become more frequent, single error correction codes are not enough and more advanced ECCs are needed. The use of advanced ECCs in memories is, however, limited by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an interesting option as the decoding is simple and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and have been recently considered to protect caches and memories. The main advantage of OLS codes is that they provide a wide range of choices for the block size and the error correction capabilities. In this brief, a method to extend OLS codes is presented. The proposed method enables the extension of the data block size that can be protected with a given number of parity bits thus reducing the overhead. The extended codes are also OS-MLD and have a similar decoding complexity to that of the original OLS codes. The proposed codes have been implemented to evaluate the circuit area and delay needed for different block sizes. [ABSTRACT FROM AUTHOR]

In this paper, a new class of (N,K) near-optimal partial Hadamard codebooks is proposed. The construction of the proposed codebooks from Hadamard matrices is based on binary row selection sequences, which are generated by quadratic residue mapping of p -ary m -sequences. The proposed codebooks have parameters and K=({p-1}/{2p})(N+\sqrt{N})+1 for an odd prime p$ and an even positive integer $n$ . We prove that the maximum magnitude of inner products between the code vectors of the proposed codebooks asymptotically achieves the Welch bound equality for sufficiently large $p$ and derive their inner product distribution. [ABSTRACT FROM PUBLISHER]

Motivated by distributed storage applications, we investigate the degree to which capacity achieving codes can be efficiently updated when a single information symbol changes, and the degree to which such codes can be efficiently repaired when a single encoded symbol is lost. Specifically, we first develop conditions under which optimum error-correction and update-efficiency are possible. We establish that the number of encoded bits that should change in response to a change in a single information bit must scale logarithmically in the block-length of the code, if we are to achieve any nontrivial rate with vanishing probability of error over the binary erasure or binary symmetric channels. Moreover, we show that there exist capacity-achieving codes with this scaling. With respect to local repairability, we develop tight upper and lower bounds on the number of remaining encoded bits that are needed to recover a single lost encoded bit. In particular, we show that when the rate of an optimal code is ε below capacity, the maximum number of codeword symbols required to recover one lost symbol must scale as log1/ε. Several variations on—and extensions of—these results are also developed, including to the problem of rate-distortion coding. [ABSTRACT FROM PUBLISHER]

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions. [ABSTRACT FROM AUTHOR]

In this work, we consider high-rate error-control systems for storage devices using multi-level per cell (MLC) NAND flash memories. Aiming at achieving a strong error-correcting capability, we propose error-control systems using block-wise parallel/serial concatenations of short Bose-Chaudhuri-Hocquenghem (BCH) codes with two iterative decoding strategies, namely, iterative hard-decision decoding (IHDD) and iterative reliability based decoding (IRBD). It will be shown that a simple but very efficient IRBD is possible by taking advantage of a unique feature of the block-wise concatenation. For tractable performance analysis and design of IHDD and IRBD at very low error rates, we derive semi-analytic approaches. The proposed error-control systems are compared with various error-control systems with well-known coding schemes such as a product code, multiple BCH codes, a single long BCH code, and low-density parity-check codes in terms of page error rates, which confirms our claim: the proposed error-control systems achieve good tradeoffs between error-performance and complexity as compared to the traditional schemes and is also very favorable for implementation. [ABSTRACT FROM PUBLISHER]

Error Correcting Code (=ECC) is a mathematical technique for reliable transmission of information over a 'noisy' communications channel which is liable to introduce errors. The theory of error correcting codes is a subfield of information theory. Employing sophisticated and efficient methods, it ensures a high probability that the messages will be read correctly even if some errors occur during transmission. The Masorah seems to carry out exactly the same function in relation to the biblical text: it appends additional data to the original text, in different forms (Masorah Magna and Masorah Parva), facilitating 'transmission' of the original text from generation to generation along with a mechanism for correcting errors that occur in the process of copying manuscripts. In this article we consider the Masorah from the point of view of modern information theory, trying to get some insights into its successes and failures by considering it as an ECC. There are clear differences between the two: while ECC usually applies to channels in which the errors occur randomly and content-blind, scribal errors are content-dependent, and the Masorah particularly focuses on protection against errors of this sort. Our study offers insights into the mechanism of the Masorah, highlighting its advantages and disadvantages. A comparison is presented between a protective mechanism which achieved great success Maimonides' codification of the tradition concerning 'open' and 'closed' portions in the Pentateuch and less successful mechanisms, such as the ancient traditions about the total number of verses in the Bible and Maimonides' codification of the graphic form in which two songs of the Pentateuch appear. The article also discusses structural aspects of the Masorah which aided the mass dissemination of the biblical text set down by the Masoretes, overcoming the problem of scribal errors, and prevailing over other textual traditions which competed with the Masoretic text. [ABSTRACT FROM AUTHOR]

Pulse position modulation (PPM) is a popular signal modulation technique which converts signals into M-ary data by means of the position of a pulse within a time interval. While PPM and its variations have great advantages in many contexts, this type of modulation is vulnerable to loss of synchronization, potentially causing a severe error floor or throughput penalty even when little or no noise is assumed. Another disadvantage is that this type of modulation typically offers no error correction mechanism on its own, making them sensitive to intersymbol interference and environmental noise. In this paper, we propose a coding theoretic variation of PPM that allows for significantly more efficient symbol and frame synchronization as well as strong error correction. The proposed scheme can be divided into a synchronization layer and a modulation layer. This makes our technique compatible with major existing techniques such as standard PPM, multipulse PPM, and expurgated PPM as well in that the scheme can be realized by adding a simple synchronization layer to one of these standard techniques. We also develop a generalization of expurgated PPM suited for the modulation layer of the proposed self-synchronizing modulation scheme. This generalized PPM can also be used as stand-alone error-correcting PPM with a larger number of available symbols. [ABSTRACT FROM AUTHOR]

. The study reported in this paper investigated the repair distribution, the error correction rates and the repair successfulness in the speech of L2 learners, with the goal to find out more information on the monitoring skills and repair behaviour. The research also included a detailed subcategory analysis within syntactic, lexical and morphological categories which have not been investigated so far. The lowest correction rates were observed in the case of morphological subcategories, showing that the speakers' attention was not oriented towards grammatical accuracy. The findings of this study may find practical application in foreign language teaching, suggesting possible reviews of formal teaching methods, aiming at more efficient linking of grammatical development to the ability to communicate. [ABSTRACT FROM AUTHOR]

Shortening is a widely used technique aiming mainly to reduce the block size of an error correcting code and at the same time to enhance its efficiency. However, due to a common misapprehension, students tend to believe that maximum shortening retains maximum coding efficiency. In this work, an educational approach is presented which eliminates the aforementioned misapprehension. Specifically, the efficiency of the shortened error correcting codes is examined both theoretically and experimentally via simulations [ABSTRACT FROM AUTHOR]

Eighteen error field correction coils (EFCCs) consisting of copper conductor and epoxy resin are installed in the vacuum vessel of JT-60SA in order to correct magnetic fields caused by manufacturing and installation errors of superconducting coils. The EFCCs are supported by pedestals made of stainless steel 316 L, and the pedestal has spring bars made of NCF625. The pedestals need to withstand electromagnetic force induced by EFCC current and magnetic field during plasma operations. They also need to allow relative displacement between the EFCC and the vacuum vessel during baking operations caused by the temperature difference between the vacuum vessel of 200 °C and EFCC of 40 °C. Diameter of the spring bars and connection structure for fixing the spring bars were designed through FEM analysis. [ABSTRACT FROM AUTHOR]

Quadratic residue (QR) codes have a high prospect on error correction for reliable data conveyance over channel with noise. This paper presents a fast algebraic scheme for decoding the binary (41, 21, 9) QR code for correcting up to 4 errors on an one-case-by-one-case basis, in which the calculation of unknown syndromes is eliminated and the conditions for checking for the various numbers of errors that exist in the received word are also simplified compared to those from Lin T. C. et al.'s algorithm, which is a traditional algebraic decoding algorithm (ADA). The computational complexity of the decoder performing the binary (41, 21, 9) QR code is analyzed thoroughly, which demonstrates that the proposed decoding scheme is faster, simpler, and more suitable for implementation than Lin T. C. et al.'s algorithm. Numerical emulation results demonstrate that the proposed decoding scheme achieves the same error-rate performance as Lin T. C. et al.'s algorithm, but it has a significantly decreased the complexity of this decoder in terms of the CPU time. [ABSTRACT FROM AUTHOR]

We examine the usefulness of applying neural networks as a variational state ansatz for many-body quantum systems in the context of quantum information-processing tasks. In the neural network state ansatz, the complex amplitude function of a quantum state is computed by a neural network. The resulting multipartite entanglement structure captured by this ansatz has proven rich enough to describe the ground states and unitary dynamics of various physical systems of interest. In the present paper, we initiate the study of neural network states in quantum information-processing tasks. We demonstrate that neural network states are capable of efficiently representing quantum codes for quantum information transmission and quantum error correction, supplying further evidence for the usefulness of neural network states to describe multipartite entanglement. In particular, we show the following main results: (a) neural network states yield quantum codes with a high coherent information for two important quantum channels, the generalized amplitude damping channel and the dephrasure channel. These codes outperform all other known codes for these channels, and cannot be found using a direct parametrization of the quantum state. (b) For the depolarizing channel, the neural network state ansatz reliably finds the best known codes given by repetition codes. (c) Neural network states can be used to represent absolutely maximally entangled states, a special type of quantum error-correcting codes. In all three cases, the neural network state ansatz provides an efficient and versatile means as a variational parametrization of these highly entangled states. [ABSTRACT FROM AUTHOR]

Quantum error correction is expected to be essential in large-scale quantum technologies. However, the substantial overhead of qubits it requires is thought to greatly limit its utility in smaller, near-term devices. Here we introduce a new family of special-purpose quantum error-correcting codes that offer an exponential reduction in overhead compared to the usual repetition code. They are tailored for a common and important source of decoherence in current experiments, whereby a register of qubits is subject to phase noise through coupling to a common fluctuator, such as a resonator or a spin defect. The smallest instance encodes one logical qubit into two physical qubits, and corrects decoherence to leading-order using a constant number of one- and two-qubit operations. More generally, while the repetition code on n qubits corrects errors to order tO(n), with t the time between recoveries, our codes correct to order tO(2n). Moreover, they are robust to model imperfections in small- and intermediate-scale devices, where they already provide substantial gains in error suppression. As a result, these hardware-efficient codes open a potential avenue for useful quantum error correction in near-term, pre-fault tolerant devices. [ABSTRACT FROM AUTHOR]

In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM) based memories are widely used in electronic systems and if their contents change due to external reasons, the electronic system can functionally fail. One of the external reasons is the radiation induced soft errors as the SRAM memories are susceptible to radiation effects. Majority of the recently proposed methods use error correction codes (ECC) to mitigate soft errors. Error correction/detection capabilities of such methods are at most 3 bits in a codeword which will be insufficient while number of memory bits affected by a radiation particle is increased, as CMOS process technology shrinks towards around 5 nm. Since memory bits affected by a radiation particle are physically close, adjacent error detection/ correction becomes a hot research topic. In this Letter, Euclidean geometry-low density parity check code, more capable ECC than Hamming code used in recent works, is explored in context of adjacent error detection performance. The results show that proposed method successfully detects up to 14-bit adjacent errors in a 15-bit codeword. As such, this method is suitable where high detection performance is needed. The proposed method is also simplified for efficient hardware implementation while detection performance is not sacrificed. Both methods are compared in terms of resource usage. [ABSTRACT FROM AUTHOR]

Summary: Cloud storage is gaining popularity as it relieves the data owners from the burden of data storage and maintenance cost. However, outsourcing data to third‐party cloud servers raise several concerns such as data availability, confidentiality, and integrity. Recently, regenerating codes have gained popularity because of their low repair bandwidth while ensuring data availability. In this paper, we propose a secure regenerating code‐based cloud storage (SRCCS) scheme, which utilizes the verifiable computation property of homomorphic encryption scheme to check the integrity of outsourced data. In this work, an error‐correcting code (ECC)–based homomorphic encryption scheme (HES) is employed to simultaneously provide data privacy as well as error correction while supporting efficient integrity verification. In SRCCS, server regeneration process is initiated on detection of data corruption events in order to ensure data availability. The ECC‐based HES significantly reduces the probability of server regeneration and minimizes the repair cost. Extensive theoretical analysis and simulation results validate the security, efficiency, and practicability of the proposed scheme. [ABSTRACT FROM AUTHOR]

An error-correcting code (ECC) immune to bit errors can make memory performance severely degraded since incomplete-word ECC write requests lead to inefficient operations on a dual in-line memory module (DIMM). A DIMM controller efficient for such ECC operations is proposed. The key idea is that read-to-write and write-toread operations caused by incomplete-word ECC write requests are split into independent read and write operations, and then the read and write operations are individually scheduled under data coherence constraints. Experimental results show that the proposed DIMM controller achieves 11% shorter memory latency, and 9.3% higher memory utilisation, on average, than the latest conventional DIMM controller in industrial multimedia applications. Moreover, it achieves up to 2.1 times higher memory performance on synthetic benchmarks. [ABSTRACT FROM AUTHOR]

An improved error code correction algorithm for phase-shifted optical quantisation is presented and experimentally demonstrated. The error probabilities for each valid code are calculated and the invalid codes are corrected by using the maximum likelihood estimation algorithm. The experimental result shows that the spur-free dynamic range of the system has an improvement of 2.28 dB compared to the Hamming algorithm in a 10-GSamples/s, 4-bit resolution all-optical analogue-to-digital converter. [ABSTRACT FROM AUTHOR]