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Summary: The intrinsic characteristics such as modular structure, filterless operation, and absence of DC‐link capacitor have made the modular multilevel converter (MMC) superior to the conventional multilevel converters. However, the submodule (SM) capacitor voltage balancing is crucial. This paper presents a voltage balance control method for MMC. The proposed method generates 2N + 1 levels (where N is the number of SMs per arm) which halves the step size of output voltage and improves the harmonic performance as compared to N + 1 level generation. It requires only one carrier per phase and no voltage and current measurements are needed for the implementation. Therefore, the proposed method makes the system cost‐effective and reduces the implementation issues related with carrier‐based methods substantially. It also alleviates the non‐uniform charge distribution problem with the phase disposition pulse width modulation (PDPWM) technique. Further, a detailed mathematical analysis is presented which enhances the understanding of balancing algorithm. In addition to this, the circulating current with 2N + 1 modulation is analyzed and a control technique is presented. The proposed voltage balancing method is simulated comprehensively in MATLAB/SIMULINK software and validated by the experimental results obtained from a laboratory prototype. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) have become prominent for high and medium power applications. The phase‐disposition pulse width modulation (PDPWM) technique is a carrier‐based method that generates good quality output. However, it has the inherent problem of uneven power distribution. Conventionally, this is solved by expensive voltage and current measurements. In this paper, a capacitor voltage balancing method is presented for MMC, which eliminates the need for voltage and current sensors. It also ensures uniform power distribution among the submodules (SMs). In addition, it needs only one carrier per phase, and one PWM reference, for either upper arm or lower arm to produce N + 1 level with N SMs per arm. The capacitor voltage balancing method is analyzed mathematically and verified for the MMC with two‐level half‐bridge SMs. The same method is also extended to the MMC with three‐level flying capacitor SMs. MATLAB/SIMULINK simulations and experimental results on a laboratory prototype are presented to verify the theoretical concepts. [ABSTRACT FROM AUTHOR]

The reliability in inverters has gained a vast importance for their enhanced economic operation of the system. This paper proposes a three-phase reliable nine-level inverter with fault ride through capability. The proposed inverter synthesizes nine levels in the output with two asymmetrical voltage sources configured at a ratio of 1:3 under healthy operation. The inverter is analyzed for open circuit faults in switches. A reliability analysis is carried out for proposed inverter and compared with classical Cascaded-H Bridge. Combined control logic is implemented to control the inverter in accordance with the operating conditions. The circuit is operated with sinusoidal pulse width modulation under healthy condition, and it is made to operate with switching frequency optimal-based pulse width modulation (SFO-PWM) under fault cases, as it enhances fundamental DC value. The proposed inverter is simulated in MATLAB/SIMULINK, and the results are validated by an experimental setup. [ABSTRACT FROM AUTHOR]

Summary: Multilevel inverter topologies have received an increasing importance for their modular structures with better integration of renewable energy sources and reduced filtering requirements. But reliability is compromised in the process of decreasing the number of switches to produce the maximum number of voltage levels. This paper elevates a single‐phase fault‐tolerant inverter topology, which is modular in structure. The proposed inverter is analyzed for open‐ or short‐circuit faults in sources and open‐circuit faults in switches. Sine Pulse Width Modulation with multicarriers technique is used to control the circuit. The carrier signals are reconfigured under fault conditions based on levels to be generated by bypassing the faulted switch or source. The circuit is simulated in MATLAB/SIMULINK, and experimental setup is developed to claim the fault tolerance of proposed inverter. [ABSTRACT FROM AUTHOR]