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We investigated the impact of mechanical stress on the cell characteristics of metal–oxide–nitride–oxide–semiconductor (MONOS) structures through experimental observations based on a curvature method for residual stress extraction and an analysis of the interface state. Residual stress induced on a substrate was observed to change from compressive to tensile depending on the tungsten process conditions; a high interface trap density was extracted under a high compressive stress environment based on a silicon bonding model. These interface trap densities were suggested as being attributable to a critical factor weakening the leakage characteristics of the MONOS structure. Besides, interface traps interrupted electron tunneling due to unintended charge trapping at the interface, which deteriorated memory characteristics indicated by a reduction in trap density. These results experimentally supported the effects of mechanical stress on device characteristics and reliability, which could be a straightforward way toward understanding the impact of stress for improved future flash memory applications. [ABSTRACT FROM AUTHOR]

String read current ( ${I}_{\textsf {read}}$ ) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated ${I}_{\textsf {read}}$ with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness ( ${T}_{\textsf {Si}}$ ), using TCAD. We find that under a critical value of GS, ${I}_{\textsf {read}}$ decreases with increase in ${T}_{\textsf {Si}}$. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which ${I}_{\textsf {read}}$ is independent of ${T}_{\textsf {Si}}$ , which is desirable to minimize the deviations in ${I}_{\textsf {read}}$ arising from ${T}_{\textsf {Si}}$ variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that ${I}_{\textsf {read}}$ increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm−2. The results presented in this paper are crucial for optimizing ${I}_{\textsf {read}}$ and program/erase threshold voltage ( ${V}_{T}$ ) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance. [ABSTRACT FROM AUTHOR]

We investigate the characteristics of a synaptic imitation device using a thin-film transistor (TFT)-type NOR flash memory cell with a half-covered floating gate. The long-term potentiation (LTP) and long-term depression (LTD) required for the operation of the spike-timing-dependent plasticity (STDP) algorithm are implemented using the proposed pulse scheme. Unsupervised learning is successfully demonstrated by applying the STDP learning rule through software MATLAB simulation reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory array. We present the learning and recognition processes of $28\times28$ MNIST handwritten digit patterns. First, STDP learning in a single-neuron string ( $784\times1$ ) is investigated, after which STDP learning is demonstrated in a multineuron array ( $784\times10$ ) with a lateral inhibition function to demonstrate the ability of multipattern learning and recognition. Meanwhile, we investigate the key factors of STDP unsupervised learning. Finally, an approach is suggested to implement a hardware neural network using the conventional CMOS technology for STDP unsupervised learning as a visual pattern recognition system. [ABSTRACT FROM AUTHOR]

Single-event-effects (SEEs) in integrated circuits (ICs) caused by galactic single ions are the major cause of anomalies for a spacecraft. The main strategies to decrease radiation failures for spacecraft are using SEEs less-sensitive devices and design radiation hardened ICs. High energy ion microbeam is one of the powerful tools to obtain spatial information of SEEs in ICs and to guide the radiation hardening design. The microbeam facility in the Institute of Modern Physics (IMP), Chinese Academy of Science (CAS) can meet both the liner energy transfer (LET) and ion range requirements for SEEs simulation experiments on ground. In order to study SEEs characteristics of ICs at this microbeam platform, a SEEs analysis system was developed. This system can target and irradiate ICs with single ions in micrometer-scale accuracy, meanwhile it acquires multi-channel SEE signals and maps the SEE sensitive regions online. A 4-Mbit NOR Flash memory was tested with this system using 2.2 GeV Kr ions, the radiation sensitive peripheral circuit regions for SEEs of 1 to 0 and 0 to 1 upset, multi-bit-upset and single event latchup have been obtained. [ABSTRACT FROM AUTHOR]

Using a test structure containing two memory cells with a shared floating gate (FG), we analyzed the processes of hot-electron-induced charge trapping in the FG oxide with a single-trap resolution. Unlike the traditional RTN-based method for single-trap study, the proposed approach allows one to detect not only the interface traps showing capture-emission events in the time domain, but also to resolve virtually all individual trapping-detrapping events in the floating gate oxide during the program-erase cycling. [ABSTRACT FROM AUTHOR]

This work reports a highly accurate test structure for high speed memories. The theoretical bases of the design are the March algorithm and cellular automata (CA) proposed by von Neumann in 1950s. Theory of 3 and 5-neighborhood CA, employed for the current application, has been developed to enhance the self-testability of memory test logic. The special class of single length cycle attractor cellular automata, introduced in this work, accepts status of each memory word and evaluates it to decide on the faults in the memory. The extension of CA neighborhood to 5 enables propagation of the effect of faults in memory or in the test logic to the error line of the test structure. This overcomes the inability of classical memory test hardware designed with the ex − or and or logic. [ABSTRACT FROM AUTHOR]