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The objective of this paper is to minimize the energy-delay product of static random access memory (SRAM) arrays by using a devicecircuit-architecture co-optimization framework. More specifically, at the device-level, high-Vt FinFETs are adopted for the 6T SRAM cell, which significantly reduces the leakage power and improves static noise margins. However, due to the lower ON current, the bitline delay of the read access is increased. Accordingly, at the circuitlevel, the voltage level of assist circuits, and at the architecture-level (i.e., the array organization), key parameters of the SRAM array are jointly optimized to derive a design that results in the minimum energy-delay product point. By using the proposed optimization framework, for SRAM array capacities ranging from 1KB to 16KB, on average 59% lower energy-delay product with maximum 12% (and on average 9%) performance penalty is achieved. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while the 8T structures have higher read currents. Also, they reveal that FinFET based structures show better read and write characteristics while consuming less static power with less variation in the presence of process variations. [ABSTRACT FROM PUBLISHER]