11 results on '"Alimohammad, Amir"'
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2. Partially binarized neural networks for efficient spike sorting
- Author
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Valencia, Daniel and Alimohammad, Amir
- Published
- 2023
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3. Towards in vivo neural decoding
- Author
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Valencia, Daniel and Alimohammad, Amir
- Published
- 2022
- Full Text
- View/download PDF
4. In vivo neural spike detection with adaptive noise estimation.
- Author
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Valencia, Daniel, Mercier, Patrick P, and Alimohammad, Amir
- Published
- 2022
- Full Text
- View/download PDF
5. Neural Spike Sorting Using Binarized Neural Networks.
- Author
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Valencia, Daniel and Alimohammad, Amir
- Subjects
APPLICATION-specific integrated circuits ,ARTIFICIAL neural networks ,GATE array circuits ,COMPLEMENTARY metal oxide semiconductors ,BIOMEDICAL signal processing - Abstract
This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- $\mu \text{m}$ CMOS process occupies 0.33 mm 2 of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates $2.02~\mu \text{W}$ of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
6. An Artificial Neural Network Processor With a Custom Instruction Set Architecture for Embedded Applications.
- Author
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Valencia, Daniel, Fard, Saeed Fouladi, and Alimohammad, Amir
- Subjects
ARTIFICIAL neural networks ,FIELD programmable gate arrays ,APPLICATION-specific integrated circuits ,SUCCESSIVE approximation analog-to-digital converters ,RECURRENT neural networks ,BIOLOGICAL neural networks ,SENTIMENT analysis - Abstract
This article presents the design and implementation of an embedded programmable processor with a custom instruction set architecture for efficient realization of artificial neural networks (ANNs). The ANN processor architecture is scalable, supporting an arbitrary number of layers and number of artificial neurons (ANs) per layer. Moreover, the processor supports ANNs with arbitrary interconnect structures among ANs to realize both feed-forward and dynamic recurrent networks. The processor architecture is customizable in which the numerical representation of inputs, outputs, and signals among ANs can be parameterized to an arbitrary fixed-point format. An ASIC implementation of the designed programmable ANN processor for networks with up to 512 ANs and 262,000 interconnects is presented and is estimated to occupy 2.23 mm2 of silicon area and consume 1.25 mW of power from a 1.6 V supply while operating at 74 MHz in a standard 32-nm CMOS technology. In order to assess and compare the efficiency of the designed ANN processor, we have designed and implemented a dedicated reconfigurable hardware architecture for the direct realization of ANNs. Characteristics and implementation results of the designed programmable ANN processor and the dedicated ANN hardware on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented and compared using two benchmarks, the MNIST benchmark using a feed-forward ANN and a movie review sentiment analysis benchmark using a recurrent neural network. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
7. Experiences in test automation for multi-client system with social media backend
- Author
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Kekkonen, Tuomas, Kanstrén, Teemu, Heikkinen, Jouni, Alimohammad, Amir, and Dini, Petre
- Subjects
model-based testing ,web service testing ,performance testing ,data validation testing ,test automation - Abstract
Effective testing of modern software-intensive systems requires different forms of test automation. This can be implemented using different types of techniques, with different requirements for their application. Each technique has a different cost associated and can address different types of needs and provide its own benefits. In this paper, we describe our experiences in implementing test automation for a multiclient application with a social media backend. As a first option, traditional scripting tools were used to test different aspects of the system. In this case, the test cases were manually defined using an underlying scripting framework to provide a degree of automation for test execution and some abstraction for test description. As a second option, a model-based testing tool was used to generate test cases that could be executed by a test harness. In this case, a generic model of the behaviour was defined at a higher abstraction level and from this large numbers of test cases were automatically generated, which were then executed by a scripting framework. We describe the benefits, costs, and other properties we observed between the two different approaches in our case.
- Published
- 2012
8. Efficient in Vivo Neural Signal Compression Using an Autoencoder-Based Neural Network.
- Author
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Valencia D, Mercier PP, and Alimohammad A
- Subjects
- Animals, Neurons physiology, Electroencephalography methods, Neural Networks, Computer, Brain-Computer Interfaces, Signal Processing, Computer-Assisted, Data Compression methods, Algorithms
- Abstract
Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.
- Published
- 2024
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9. An Efficient Brain-Switch for Asynchronous Brain-Computer Interfaces.
- Author
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Valencia D, Mercier PP, and Alimohammad A
- Abstract
Intracortical brain computer interfaces (iBCIs) utilizing extracellular recordings mainly employ in vivo signal processing application-specific integrated circuits (ASICs) to detect action potentials (spikes). Conventionally, "brain-switches" based on spiking activity have been employed to realize asynchronous (self-paced) iBCIs, estimating when the user involves in the underlying BCI task. Several studies have demonstrated that local field potentials (LFPs) can effectively replace action potentials, drastically reducing the power consumption and processing requirements of in vivo ASICs. This article presents the first LFP-based brain-switch design and implementation using gated recurrent neural networks (RNNs). Compared to the previously reported brain-switches, our design requires no exhaustive learning phase for the estimation of optimal recording channels or frequency band selection, making it more applicable to practical asynchronous iBCIs. The synthesized ASIC of the designed in vivo LFP-based feature extraction unit, in a standard 180-nm CMOS process, occupies only 0.09 mm
2 of silicon area, and the post place-and-route synthesis results indicate that it consumes 91.87 nW of power while operating at 2 kHz. Compared to the previously published ASICs, the proposed LFP-based brain-switch consumes the least power for in vivo digital signal processing and achieves comparable state estimation performance to that of spike-based brain-switches.- Published
- 2024
- Full Text
- View/download PDF
10. Power-efficient in vivo brain-machine interfaces via brain-state estimation.
- Author
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Valencia D, Leone G, Keller N, Mercier PP, and Alimohammad A
- Subjects
- Brain, Prostheses and Implants, Computers, Quality of Life, Brain-Computer Interfaces
- Abstract
Objective. Advances in brain-machine interfaces (BMIs) can potentially improve the quality of life of millions of users with spinal cord injury or other neurological disorders by allowing them to interact with the physical environment at their will. Approach. To reduce the power consumption of the brain-implanted interface, this article presents the first hardware realization of an in vivo intention-aware interface via brain-state estimation. Main Results. It is shown that incorporating brain-state estimation reduces the in vivo power consumption and reduces total energy dissipation by over 1.8× compared to those of the current systems, enabling longer better life for implanted circuits. The synthesized application-specific integrated circuit (ASIC) of the designed intention-aware multi-unit spike detection system in a standard 180 nm CMOS process occupies 0.03 mm
2 of silicon area and consumes 0.63 µ W of power per channel, which is the least power consumption among the current in vivo ASIC realizations. Significance. The proposed interface is the first practical approach towards realizing asynchronous BMIs while reducing the power consumption of the BMI interface and enhancing neural decoding performance compared to those of the conventional synchronous BMIs., (Creative Commons Attribution license.)- Published
- 2023
- Full Text
- View/download PDF
11. Partially binarized neural networks for efficient spike sorting.
- Author
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Valencia D and Alimohammad A
- Abstract
While brain-implantable neural spike sorting can be realized using efficient algorithms, the presence of noise may make it difficult to maintain high-peformance sorting using conventional techniques. In this article, we explore the use of partially binarized neural networks (PBNNs), to the best of our knowledge for the first time, for sorting of neural spike feature vectors. It is shown that compared to the waveform template-based methods, PBNNs offer robust spike sorting over various datasets and noise levels. The ASIC implementation of the PBNN-based spike sorting system in a standard 180-nm CMOS process is presented. The post place and route simulations results show that the synthesized PBNN consumes only 0.59 μ W of power from a 1.8 V supply while operating at 24 kHz and occupies 0.15 mm 2 of silicon area. It is shown that the designed PBNN-based spike sorting system not only offers comparable accuracy to the state-of-the-art spike sorting systems over various noise levels and datasets, it also occupies a smaller silicon area and consumes less power and energy. This makes PBNNs a viable alternative towards the implementation of brain-implantable spike sorting systems., Competing Interests: Conflict of interestThe authors have no competing interests to declare., (© Korean Society of Medical and Biological Engineering 2022, Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.)
- Published
- 2022
- Full Text
- View/download PDF
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