1. Power and area optimization for run-time reconfiguration system on programmable chip based on magnetic random access memory
- Author
-
Zhao, Weisheng, Belhaire, Eric, Chappert, Claude, and Mazoyer, Pascale
- Subjects
MRAM (Computer memory) -- Design and construction ,MRAM (Computer memory) -- Properties ,Integrated circuits -- Design and construction ,Integrated circuits -- Usage ,Semiconductor chips -- Design and construction ,Semiconductor chips -- Usage ,Digital integrated circuits -- Research ,Switching circuits -- Research ,Standard IC ,Programmable logic array ,Business ,Electronics ,Electronics and electrical industries - Abstract
In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model. Index Terms--Flip-flop, FPGA, low power and low die area, LUT, MRAM, nonvolatile, run-time reconfiguration, SOPC.
- Published
- 2009