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The threshold voltage variability of the select transistors is an important issue in the development of 3-D NAND flash memory. Particularly, pillar-to-pillar variations in threshold voltage (VT) of the ground select transistor (GST) are critical across the wafer. The VT variation is attributed to the nonuniformity in the plug height of the epitaxially grown silicon layers in different pillars. In this article, we propose different techniques to achieve performance uniformity in different strings across the wafer in terms of VT distribution of GST. We show that by optimizing the channel doping and gate metal work function (WF) of the GST, the NAND string VT nonuniformity can be eliminated. It is also shown that VT variability can be further minimized by optimizing GST gate length. Further, we present a two-MOSFET model for the pillar-to-pillar VT variation across the wafer. This study provides important results for designing 3-D NAND memories with higher performance uniformity for the pillar-to-pillar variations in strings across the wafer. [ABSTRACT FROM AUTHOR]

The channel tapering from top to bottom in vertical channel 3-D NAND is a major concern. This leads to nonuniformity in the NAND string performance, including cell current (Icell) and threshold voltage (VT) variation along the vertical NAND string. In this article, we show that the variation in the electric field due to the difference in the channel radius from bottom to top is the root cause behind the VT variation along the string. For the first time, we propose novel techniques to minimize the adverse effects of the channel tapering on VT variations. It is shown that graded channel doping (~1018 cm−3 at the bottom to ~1015 cm−3 at the top) results in the narrowing of the VT variation by ~90% along the vertical string. Further, we propose that a nonuniform block oxide thickness along the string can be used to enhanced uniformity of VT distribution from bottom to top. Additionally, we investigate and show that the uniformity in VT distribution among word line (WL) transistors can also be achieved by optimizing the amplitude and duration of the position-dependent program/erase voltages. The proposed techniques in this article have a high potential for designing variation tolerant and reliable 3-D NAND memories having enhanced uniformity in the program/erase VTand Icell distribution. [ABSTRACT FROM AUTHOR]

String read current ( ${I}_{\textsf {read}}$ ) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated ${I}_{\textsf {read}}$ with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness ( ${T}_{\textsf {Si}}$ ), using TCAD. We find that under a critical value of GS, ${I}_{\textsf {read}}$ decreases with increase in ${T}_{\textsf {Si}}$. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which ${I}_{\textsf {read}}$ is independent of ${T}_{\textsf {Si}}$ , which is desirable to minimize the deviations in ${I}_{\textsf {read}}$ arising from ${T}_{\textsf {Si}}$ variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that ${I}_{\textsf {read}}$ increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm−2. The results presented in this paper are crucial for optimizing ${I}_{\textsf {read}}$ and program/erase threshold voltage ( ${V}_{T}$ ) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance. [ABSTRACT FROM AUTHOR]