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This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 x 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 x 2 array demonstrates a 200-MHz locking range and 1 x 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below -100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors' knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process. Index Terms--BiCMOS integrated circuits, coupled oscillator, mutual injection locking, phased arrays.

We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the system's unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5 % error. Index Terms--Data-dependent jitter (DDJ), deterministic jitter (DJ), jitter, jitter distribution, linear time-invariant (LTI) system, step response.

Coupled phase-locked loops (CPLLs) are introduced as novel circuits for phased-array antennas. Successful implementation relies on characterizing the synchronization behavior of CPLL circuits over a broad range of circuit parameters. Considering inherent time delay in the phase-locked loop demonstrates the degradation in the pull-in and hold-in ranges, as well as circuit instabilities, suggesting circuit parameter limits in a phased-array design. We compare the theoretical limits, in the form of analytic equations and numerical simulations, with measurements of the pull-in and hold-in processes of a 1.5-GHz prototype CPLL. Index Terms--Coupled phase-locked loop (CPLL), hold-in range, pull-in range, time delay.

We present an interpretation of conventional figure-of-merit (FOM) and average input-referred noise current density (IRNCD) that characterizes optical receivers to determine how technologies and circuits best address energy efficiency. A design methodology is presented for differential optical receivers based on Cherry-Hooper Emitter Follower (CHEF) front-end designs targeting 56-Gbps applications is realized in a 130-nm SiGe BiCMOS process. The electrical measurements in a 50- $\Omega$ environment demonstrate data rates up to 112 Gbps and 84 Gbps for two design variants. In an open input and maximum gain configuration, the rms input referred noise currents are 3.59 $\mu$ $A_{RMS}$ and 2.41 $\mu$ $A_{RMS}$ and the corresponding average input referred noise current densities are 17.25 $pA/\sqrt{Hz}$ and 12.86 $pA/\sqrt{Hz}$. The packaged electro-optical measurements of the receiver variants is carried out with a single commercial off-the-shelf (COTS) photodetector demonstrate open eyes at data rates up to 64 Gbps. At 60 Gbps, the receiver variants achieve a $BER < 10^{-10}$ and $BER < 10^{-9}$. The total power consumption for the variants are 162 mW and 138 mW for overall energy efficiencies (with respect to electro-optical performance) of 2.53 $pJ/bit$ and 2.3 $pJ/bit$. [ABSTRACT FROM AUTHOR]

This article presents a full-duplex (FD) rake receiver (RX) that uses the orthogonality properties of pseudo-noise (PN) codes to reject transmitter (TX) self-interference (SI) in the RF domain, allowing simultaneous transmit and receive (STAR) operation in the same frequency channel. The rake RX also exploits multipath propagation in wireless channels and PN code orthogonality to gather signals across multipath components to increase the signal-to-noise ratio (SNR) while avoiding the fading effects of multipath channels. The rake RX shares a low-noise amplifier (LNA) between the three rake fingers and a high-linearity baseband (BB) section with the second-order filtering to improve the rejection with low power consumption. Measurements indicate that TX SI rejection is 41.2 dB in the RF domain with 9-dB SNR improvement in a multipath channel. The rake RX is implemented in a 45-nm RFSOI CMOS process and occupies an active area of 1.6 mm2 while consuming 45.8 mW per finger, including clock power consumption. [ABSTRACT FROM AUTHOR]

RF photonic components suffer from poor spurious-free dynamic range (SFDR) due to the high noise and distortion generated by a silicon photonic (SiP) Mach–Zehnder modulator (MZM). This work demonstrates a distributed silicon–germanium (SiGe) heterojunction bipolar transistor (HBT)-based low-noise amplifier (LNA) co-designed for linearization with a SiP MZM for a broadband radio-over-fiber (RoF) link. The SiGe LNA incorporates a distributed, tunable predistortion scheme that is inherently wideband and improves the third-order intercept point over an 18-GHz range. The assembled SiGe LNA and SiP MZM prototype demonstrates an SFDR as high as 120 dB ⋅ Hz2/3 at 9 GHz, a 14-dB improvement over previous SiP RF components or RoF links. [ABSTRACT FROM AUTHOR]

As datacenters continue to scale in size, energy efficiency for short reach (<2 km) links is a major factor for networks that may connect hundreds of thousands of servers. We demonstrate that links based on analog coherent detection (ACD) offer a promising path to simultaneously achieving significantly larger link budgets and improved link energy efficiency. A complete analysis is presented that considers the power consumption of all the photonic and electronic components necessary to realize an ACD link architecture based on 50 Gbaud (GBd) quadrature phase-shift keying (QPSK) signaling combined with polarization multiplexing to achieve 200 Gb/s/λ. These links utilize receivers that incorporate an optical phase-locked loop (OPLL) to frequency- and phase-lock the local oscillator (LO) laser to the incoming signal. QPSK modulation offers compelling advantages both in achievable link budget and in energy efficiency. Indeed, low-complexity electronics based on limiting amplifiers can be used as opposed to the linear front-ends, A/D converters, and digital signal processing (DSP) required for higher-order QAM or PAM formats. Our analysis indicates that links with 13 dB of unallocated budget operating at error rates of <10−12 can be achieved and is compatible with higher error rates that require forward error correction (FEC). We present a comparison of silicon and InP platforms and evaluate both traveling-wave and segmented modulator designs, providing an illustration of the wide design space before converging on the most promising architectures that maximize energy efficiency and minimize laser power. We establish the theoretical potential to achieve picojoule-per-bit energy efficiency targets. [ABSTRACT FROM AUTHOR]

We present a comparison of design trade-offs for transimpedance, sensitivity, DC voltage offset cancellation, group-delay variation (GDV), common-mode rejection, and overload for transimpedance amplifiers (TIA) based on balanced, unbalanced, and pseudodifferential topologies. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results shown here support data rates to 50 Gb/s with BER better than 10−10. The power consumption of the TIAs is 54 mW for TIA designs that approach 1 pJ/b. [ABSTRACT FROM AUTHOR]

Collective pulse oscillators (CPOs) are novel designs constructed using pulse regenerative amplifiers that exhibit time-variant gate delay based on the residual charge from past state. This property makes it possible to achieve precise phase resolutions smaller than a pulse gate delay and/or provide identical phase taps at multiple physical locations. CPOs exhibit temporal phase error correction that results in an improvement in frequency stability $\propto -10\log p$ for power $\propto p$ across all timescales beyond the correction settling time. While CPOs result in device noise-based figure of merits (FoMs) comparable to that of ring oscillators, they are more resilient to power-coupled and impulse noise. This article presents a systematic time-domain analysis of the properties of CPOs based on an abstract model that captures the time-variant delay of pulse gates. Closed-form analytic solutions for CPOs disturbed by impulse noise are derived, and higher order CPOs with continuous noise injection are analyzed using behavioral simulations and characterized using Allan deviation. Hspice simulation results are presented to validate the model and compare CPOs with ring oscillators. Allan deviation and phase noise measurements on CPOs of 8 and 40 gates fabricated in GFUS8RF (130-nm) technology corroborate the theory and simulation results. [ABSTRACT FROM AUTHOR]

Though GaN HEMTs have primarily been used for power amplification, they are also well suited for receiver applications. In the front-end of receivers, non-linearities, in particular third-order intermodulation products lead to in-band signal distortion. The intermodulation distortion is primarily dominated by transconductance and its derivatives. In this paper, we report on N-polar GaN MIS-HEMTs able to simultaneously achieve high gain (12.7 dB) and excellent linearity performance (OIP3/PDC of 15 dB) for low-power receiver application at 30 GHz. With a two-tone load-pull input-bias sweep, we demonstrate that the linearity of high performance HEMTs is sensitive to bias, and we present our measurement methodology to accommodate this. [ABSTRACT FROM AUTHOR]

A code-domain transceiver front end that incorporates a transmit modulator and a receive (RX) RF signal correlator is presented. An integrate-and-dump $N$ -path filter improves rejection by 8 dB. We propose an RF chopper switch with 12.1-/23.1-dBm P1dB/IIP3 for both RF correlation and filtering that rejects TX self-interference by 49.5 dB. Walsh and Barker codes are generated with fine and coarse tuning for synchronization. The RX power consumption is 18 mW, including dynamic power (1-V supply) and four analog amplifiers (1.5 V) at the operating frequency of 1 GHz and the code rate of 200 megachip-per-second (Mc/s). The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Mc/s. Over the air testing demonstrates synchronization with Barker codes. [ABSTRACT FROM AUTHOR]

High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc. [ABSTRACT FROM AUTHOR]

Due to the heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. Thus, performing the array processing in a power-efficient manner is a fundamental challenge. Analog and hybrid BF require few analog-to-digital and digital-to-analog converters (ADCs and DACs), but can only communicate in a small number of directions at a time, limiting directional search, spatial multiplexing, and control signaling. Digital BF enables flexible spatial processing but must be operated at a low quantization resolution to stay within reasonable power levels. This decrease in quantizer resolution distorts the received as well as the transmitted signal. To assess the effect of coarse quantization at the receiver, this paper presents a system level analytic framework based on a simple additive quantization noise model (AQNM). The analysis verified through extensive simulations reveals that at moderate resolutions (3–4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low resolution ADCs limit the high SNR, where cellular systems typically do not operate. For the transmitter, it is shown that DACs with 4 or more bits of resolution can support high order modulations, and do not violate the adjacent carrier leakage limit set by 3rd Generation Partnership Project (3GPP) New Radio (NR) standards for cellular operations. In fact, our findings suggest that low resolution digital BF architectures can be a power-efficient alternative to analog or hybrid BF for both transmitters and receivers at millimeter-wave. [ABSTRACT FROM AUTHOR]

This article demonstrates a signal processing technique for receiving non-contiguous RF channels by concurrently mixing several RF bands to adjacent IF channels. Consequently, channel selection does not require local oscillator tuning and the proposed receiver (RX) can switch channels in less than 25 ns. The RX chip operates over a frequency range of 100 MHz–1.4 GHz and demonstrates an out-of-band rejection of 49 dB and a measured RX sensitivity of −86 dBm, which is the lowest measured for $N$ -path-based RXs. The chip was fabricated in a 45-nm RF silicon-on-insulator (SOI) CMOS process and occupies an active area of 0.55 mm2 with the power consumption of 23.1 mW when operating at 1 GHz. The chip performance is verified with over-the-air measurement of two transmitted signals 80 MHz apart that are received simultaneously with a 10-MHz analog-to-digital converter (ADC) at an error vector magnitude (EVM) around −20 dB. The measured dynamic range for EVM less than −20 dB is better than 86 dB for a QPSK constellation. [ABSTRACT FROM AUTHOR]

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch. [ABSTRACT FROM AUTHOR]

The dynamic range of a radio-over-fiber (RoF) link is fundamentally limited by the linearity of electro-optic modulators. Silicon photonic (SiP) processes offer significant potential for integration, but the plasma dispersion effect impacts the realizable spur-free dynamic range (SFDR). This article analyzes the underlying source of nonlinearity in SiP Mach–Zehnder modulator (MZM) and demonstrates fundamental limitations on intermodulation distortion. A SiGe low-noise distributed driver is co-designed for the SiP MZM to linearize and extend the bandwidth over which the SFDR remains high. The RoF transmitter achieves 1–20 GHz bandwidth and an SFDR of 109 dB $\cdot $ Hz2/3 at 11 GHz. To the best of our knowledge, this is the highest SFDR demonstrated for a SiP technology without incorporating predistortion. [ABSTRACT FROM AUTHOR]

Silicon photonics offer a low-cost platform for large-scale RF system integration. Spur-free dynamic range (SFDR) for analog and RF photonic components is limited by electrical and optical characteristics of the p- and n- junction used to produce plasma dispersion. We propose a silicon ring modulator and demonstrate design conditions that balance the phase change between the DC Kerr and plasma dispersion effects to produce a broadband, linear electro-optical conversion. A linear phase shifter is tested within a ring modulator and an SFDR of 98 dB $\cdot$ Hz $^{2/3}$ is measured. With predistortion, the SFDR increases to 108 dB $\cdot$ Hz $^{2/3}$. In addition, the ring supports discrete multitone modulation with 16-QAM subcarriers at a 47 Gbps data rate over a 16 GHz bandwidth. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

Two $K_{u}$ - to V-band distributed amplifiers (DAs) based on nMOS and nMOS/pMOS gain stages and a distributed transceiver front end (DTFE) are presented for ultra-wideband power and low-noise amplification in a 45-nm RF CMOS silicon-on-insulator (SOI) technology. Supply scaling of gain stages through high-pass filter sections achieves high efficiency while maintaining a broadband 50- $\Omega $ match. The nMOS DA has a gain of 13 dB over a 3-dB bandwidth of 10–82 GHz and a minimum noise figure (NF) of 5.3 dB. The measured peak output power is 17.2 dBm with a peak power-added efficiency (PAE) of 17.4% at 50 GHz. The hybrid DA allows higher operating voltage and distortion cancelation of scaled pMOS devices to an achieve output power of 17.5 dBm with PAE of 20.2% and low third-order intermodulation and amplitude–phase nonlinearities. The DTFE utilizes time-domain duplexing to drive a shared antenna port for transmit (TX) and receive (RX) modes. It achieves TX gain of 11.7 dB from 12–76 GHz with peak output power of 17 dBm and PAE of 14.2%. RX gain is 9 dB from 11–77 GHz with a minimum NF of 6.2 dB. The 5-GHz wideband 16-QAM is demonstrated in the amplifier circuits for data rates exceeding 20 Gb/s. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

This paper presents an explicit analysis of the bandwidth and port imbalance of a subquarter-wavelength transmission-line (t-line) transformer and verifies this with the design of a two-stage D-band power amplifier (PA). Series power combining techniques incorporate both stacked heterojunction bipolar transistors (HBTs) and power combining using an 8-way sub-quarter-wavelength t-line transformer above 100 GHz. The extremely compact power combining methodology leads to a small die area of 0.62 mm2 and a record 254-mW/mm2 output power per unit die area. The PA has been fabricated in a 90-nm silicon germanium BiCMOS technology and produces more than 21-dBm output power over the frequency range of 114–130 GHz with a peak output power of $160~{\mathrm{mW}}\approx 22~{\mathrm{ dBm}}$ at 120 GHz and a 3-dB small-signal bandwidth of 35 GHz. This output power is 32% higher than the highest prior art, while the chip area is 77% smaller. [ABSTRACT FROM AUTHOR]

This brief studies the frequency drift due to temperature variation in LC CMOS quadrature oscillators. The quadrature oscillators, which can oscillate in two modes at different frequencies, have different temperature behavior in the two modes, with one mode showing lower sensitivity to temperature variation. Simulation results of a series coupled quadrature oscillator confirm that the mode with higher frequency is more stable to temperature variation. The measurement results of the fabricated chip in a 90-nm CMOS technology verifies the analysis. The optimized frequency drift is ±100 ppm across temperature 0–60 °C) for an oscillation frequency of 5 GHz with −118 dBc/Hz phase noise at 1 MHz offset frequency while consuming 8 mA from a power supply of 1.2 V. [ABSTRACT FROM AUTHOR]

An image-selection, two-element transceiver is presented that operates over a large fractional bandwidth (FBW) covering both 71–76 and 81–86 GHz while requiring only 3 GHz of local oscillator (LO) tuning range at the RF mixer. A bidirectional sliding-intermediate frequency (IF) Weaver architecture allows operation in either transmit (TX) or receive (RX) modes. The sliding IF and narrow LO tuning range allow wideband image rejection using only a single-stage polyphase filter. The circuit is implemented in a 90-nm SiGe BiCMOS process and the RF and LO circuitry consume at most 150 and 250 mW, respectively. Measurements show less than ±0.75-dB gain variation over 10 GHz in the TX mode and less than ±1-dB variation over 10-GHz bandwidth in the RX mode. With 16- and 64-quadrature-amplitude modulation (QAM), the error vector magnitude is below −22 and −28.5 dB at the data rates of 12 and 9 Gb/s, respectively. [ABSTRACT FROM AUTHOR]

A fully integrated CMOS power amplifier (PA) that efficiently generates high-voltage RF waveforms directly from a 4.8-V supply using only low-voltage thin-oxide transistors is introduced. High-voltage operation is achieved via implicit ~100% efficient dc–dc conversion enabled by stacking and flying individual class-D PA cells in a House-of-Cards (HoC) topology. By dynamically reconfiguring digitally controlled HoC slices to support different voltage conversion ratios and capacitively coupling their outputs, a Doherty-like high-efficiency backoff profile is achieved without using any magnetic impedance inverter. A test chip, implemented in 65-nm low-power CMOS, operates directly from 4.8 V using only 1.2-V transistors, and attains above 40% battery-to-RF efficiency at both 23-dBm peak power and at 6-dB backoff at 720 MHz. When applying a 10-MHz 16-quadrature amplitude modulation signal, the PA achieves an error vector magnitude of 3.6%-rms without using any predistortion techniques with an average output power and power-added efficiency of 15.7 dBm and 26.5%. [ABSTRACT FROM AUTHOR]

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°. [ABSTRACT FROM PUBLISHER]

This paper presents the first phased array transceiver operating from 71 to 86 GHz using injection-locked oscillators (ILOs) for phase shifting. A folded-cascode ILO is proposed to extend the locking range of an array of oscillators. Frequency multiplication covers a 10-GHz tuning range with 23-dB power gain. Each ILO path covers more than ±300° and exhibits low amplitude variation with respect to phase shift range (<1 dB) and excellent isolation and amplitude error (<0.5 dB) between array elements. A wideband, bidirectional RF front end delivers 10-dBm maximum output power with more than 20-dB conversion gain over the 3-dB bandwidth in the transmit (TX) mode and a minimum 9.5-dB noise figure with more than 20-dB conversion gain in the receive (RX) mode. Low phase noise is demonstrated in the ILO approach over the phase tuning range with −112 dBc/Hz at 1-MHz offset and phase noise variation for different phase shift states under 2.5 dB, corresponding to less than 2° phase error. Array patterns demonstrate the wide scan range, and dynamic measurements show that the transmitter supports up to 6-Gb/s data rate with 256 QAM. The chip has $3.4\times2.1$ mm2 area implementing in the 90-nm BiCMOS technology and consuming 386.4 mW in the TX mode and 286 mW in the RX mode per element. [ABSTRACT FROM AUTHOR]

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is 1.5~\text {mm}\times 0.9 mm including pads. [ABSTRACT FROM AUTHOR]

A wideband technique for outphasing modulation is introduced that efficiently generates outphasing modulation using differential injection locking between oscillators without requiring digital signal processing. Complex modulation with outphasing signals is demonstrated with two edge oscillators generating outphasing signals locked to a central master oscillator. The coupled-oscillator outphasing modulator circuit is implemented in 45 nm SOI CMOS and delivers 9.2 dBm to a 50 $\Omega $ external load at 8 GHz while consuming only 36.5 mW to achieve a 22.7% overall system efficiency. The modulator provides 30 dB of dynamic range and the measurements demonstrate complex waveforms such as 64-quadrature amplitude modulation with 2.1% error vector magnitude at 60 Mb/s. [ABSTRACT FROM AUTHOR]

To increase the voltage handling capability of scaled CMOS-based circuits, series connection (stacking) of transistors has been demonstrated in recently reported mm-wave power amplifiers. This paper discusses the implementation of stacked CMOS circuits employing a compact, multigate layout technique, rather than the conventional series connection of individual transistors. A unit multigate FET is composed of a single transistor with one source and drain and multiple (four) gate connections. Capacitances are implemented in a distributed manner allowing close proximity to the individual gate fingers using metal layers available within the CMOS back-end-of-line (BEOL) stack. The multigate structure is demonstrated to decrease parasitic resistances and capacitances, and has better layout for heat-sinking. The unit cell is replicated through tiling to implement larger effective gate widths. Millimeter-wave power amplifiers using the multigate-cell are presented which operate over the 25–35 GHz band and achieve 300 mW of saturated output power and peak power-added efficiency (PAE) of 30% in 45 nm CMOS SOI technology. To the authors’ knowledge, the output power is the best reported for a single stage CMOS power amplifier that does not use power-combining for this frequency range. [ABSTRACT FROM AUTHOR]

A series code selective filter (CSF) for full-duplex communication is presented. The CSF passes a desired signal in a frequency band only when the signal is tagged with a pseudonoise (PN) code that matches the code at the filter. This approach is shown to reject a transmit signal in the same band as a desired receive signal. The coded transmitter signal is orthogonal through appropriate code selection from a codebook and the PN sequence spreads the signal energy outside the filter bandwidth (BW). The CSF achieves a self-interference rejection of 23.2 dB over a 10-MHz BW using on-chip generated Walsh codes. The CSF operates from 300 to 675 MHz and consumes 28.2 mA from a 1-V supply at 500 MHz. The CSF achieves an IIP3 of 15.7 dBm. The CSF was implemented in a 45-nm CMOS silicon on insulator process and occupies an area of 0.9 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a dual-mode intermediate frequency (IF) signal processing circuit for pulse compression radar (PCR) and symbol recovery. A half-duplex architecture is proposed to support modulation and demodulation of PCR signals. For data communication, the modulator and the demodulator support up to 3-Gb/s QPSK signal. For range sensing, the proposed IF correlation technique supports 1.5-GHz bandwidth (BW) and 3/5/7-b Barker codes for 10-cm range resolution. The circuit includes a high-linearity switch, a modulator, a reconfigurable demodulator/correlator, and an in-phase and quadrature clock signal generator. This proposed system is fabricated with 90-nm CMOS, and each channel can be configured to operate from 200 Mb/s to 1.5 Gb/s with different Barker codes. The maximum power consumption is 54 mW with 1.5-GHz BW (10 cm) in range sensing mode and 49 mW at a rate of 3 Gb/s in data communication mode. [ABSTRACT FROM PUBLISHER]

This paper presents a link analysis for optical interconnects based on CMOS scaling toward FinFET devices. An on-chip wavelength division multiplexing (WDM) link is modeled assuming silicon photonic ring modulators, WDM multiplexers and demultiplexers, and photodetectors. A high-speed CMOS transceiver is designed and evaluated using 28-nm FD-SOI and 14-nm FinFET processes. Compared to 28-nm FD-SOI, the 14-nm FinFET offers higher intrinsic gain and allows for 50% higher transconductance per drain current suggesting more energy-efficient circuit design. Cosimulation of the photonic and electronic devices demonstrates an optimum energy efficiency of \sim 2\, \textpJ/b at 25\, \textGb/s for a bit-error rate of 10^-12 including laser and ring tuning power. [ABSTRACT FROM PUBLISHER]

A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid N-path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A gm2{\mathchar"702D}gm3 cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. [ABSTRACT FROM PUBLISHER]

Double-edged pulsewidth modulation (DPWM) is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with 10^-12 bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead. [ABSTRACT FROM AUTHOR]

Quadrature oscillators (QOs) based on parallel or series coupling mechanisms produce ambiguous phase relationships between the coupled oscillators. Deterministic mode selection is presented and analyzed for a series-coupled LC quadrature oscillator (LC-QO) and leveraged to increase the tuning range of the QO. Series-coupled LC-QOs have been implemented in a 90-nm CMOS technology. Measured results show a frequency tuning range of 94% for a center frequency of 1.3 GHz, 60% for the oscillator operating at 3.7 GHz, and 52% for the oscillator operating at 4.4 GHz. [ABSTRACT FROM PUBLISHER]

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50-\Omega interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than -53 dBc HD_3 at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel. [ABSTRACT FROM PUBLISHER]

A tunable N-path filter with more than one decade tuning range is demonstrated to address transmit (TX) leakage in a surface-acoustic-wave-less diversity path receiver for frequency-division duplexing cellular systems. The proposed filter simultaneously creates a reject band and passband anywhere from 0.2 to 3.6 GHz to suppress TX leakage while minimizing insertion loss of the receive signal and is implemented in 45-nm CMOS silicon-on-insulator. Measurements show the 3-dB bandwidth of the passband is greater than 80 MHz with an independently tunable reject band, providing the ultimate rejection is from 33 to 41 dB while the passband insertion loss is between 2.6 dB and 4.3 dB over the tuning range. The proposed filter offers 29-dBm out-of-band (OOB) third-order input-intercept power (IIP3) and 22-dBm in-band (IB) IIP3 with a 10-dBm blocker 1-dB compression point (B1dB). To the authors’ knowledge, this is the highest B1dB, IB IIP3, and OOB IIP3 for a CMOS tunable filter. [ABSTRACT FROM PUBLISHER]

Circulators and quasi-circulators (QCs) have a tradeoff between maximum isolation and bandwidth. We present a tunable distributed active circuit to achieve high isolation over a wide frequency range. The reported QC provides more than 40-dB suppression between transmit (TX) output signal at the antenna and TX leakage into the receive (RX) port over a tuning range of 5.3–7.3 GHz in small-signal operation. Large-signal TX-RX suppression is optimized across power level. The TX output achieves peak power of 18 dBm and 12% power-added efficiency at 6.3 GHz. The QC is designed in a high-resistivity 45-nm CMOS silicon-on-insulator process and occupies an area of 1.62~ \text mm \times 0.97~ \text mm . [ABSTRACT FROM PUBLISHER]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]