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Nowadays, more than 180 countries including China, Japan, EU and others have signed the Kyoto Protocol, then “Energy-saving and Carbon reduction” becomes a popular slogan and an important mission to protect the environment and to pursue the national sustainability. Taiwan government is making many environmental policies as well for driving the people to purchase the eco-products like electric car, hybrid car and household appliances to reach the goal of Carbon reduction, and the industries are also actively involved in the mass production of the key components such as high power IGBT modules for EV/HEV, intelligent power module (IPM) for air-conditioner, and MOSFET SiP modules for the power management of consumer electronics and hand-held machine tools. The first 600 V/450 A IGBT module for EV/HEV application developed by ITRI was announced in this work. The module was composed of IGBTs and freewheel diodes (FWD), firstly 2 IGBTs and 2 FWDs were attached on one Al2O3 direct bonded copper (DBC) substrate by a Pb-free solder perform with a thickness of 100 μm in a vacuum reflow oven, and 3 DBCs were then soldered on a Cu baseplate by a solder perform as well. After cleaning, a heavy Al wire was used to connect the devices and DBCs, and subsequently the housing was adhered to the Cu baseplate by an adhesive. Finally, a Si gel with a dielectric strength higher than 10 kV/mm was poured for insulation and then agglutinated by heating. The process conditions were optimized in this study, a die shear strength higher than 20 MPa was acquired after optimizing the reflow profile, and a design of experiments (DoEs) plan was executed to obtain a pull strength higher than 800 g for the heavy Al wire bonding. After temperature cycling for 1000 times, the loss of the strengths was less than 20%, and the long-term reliability of the power module was verified [ABSTRACT FROM PUBLISHER]

Due to the raising requirements of functionality and performance in consumer electronics, high density package technology including high I/O interconnections and 3D chip-stacking technology have received a great number of attentions. Solder micro bumps are widely applied in high density interconnections packaging, but its bonding temperature is still high during process. During chip stacking process, high bonding temperature would lead chip damage and chip warpage induced by the mismatch of coefficient of thermal expansion among each structure within the chip. Also, warpage would cause stress concentration happened within the chip and damage the device and micro interconnections. In order to meet the purpose of low temperature bonding, we demonstrated the chip-to-chip stacking module with a bump pitch of 30um by using non-conductive film in this study. The reliability of the chip-stacking module produced by such low temperature bonding approach was also estimated. A chip-on-chip (COC) structure was used as the test vehicles. There were about 3000 bumps totally in this test vehicle. For evaluating the feasibility of adhesive bonding by NCF in fine pitch micro bumps, Cu/Ni/Au micro bumps joined with Cu/Sn solder micro bumps was conducted by using NCF in this study. After assembly process, thermal cycling test, thermal humidity storage test and high current test were carried out to evaluate the reliability performance of the micro interconnections by such low temperature bonding approach. In this investigation, the chip-on-chip stacking module with a bump pitch of 30μm by using non-conductive film was achieved. The bonding results revealed that the contact resistance of micro joints was about 100 ∼ 350 MΩ. The high deviation of contact resistance was due to the non-melting contact between joined micro bump by soft tin solder. The reliability results revealed that the chip-stacking module produced by NCF could pass the reliability test of 1000 cycles of TCT and 1000 hours of THST. The results of high current test also showed that the NCF joint had excellence endurance against high current density of 5×104 A/cm2 for more than 1300 hours with an increase of contact resistance less than 2%. This study displayed that the NCF material had great potential to be applied in fine-pitch 3D chip stacking. The multi-chip stacking module with a TSV pitch of 20μm produced by NCF will also be presented in this investigation. [ABSTRACT FROM PUBLISHER]

With the increased demand of functionality in electronic device, three dimensional integration circuits technology together with downscaling of interconnection pitch present an important role for the development of next generation electronics. In the current types of interconnects, solder micro bumps have received much attention due to its low cost in material and process. For fine pitch solder micro bump interconnections, selection of under bump metallurgical material is a crucial issue because the UBM structure/material will show a significant influence on the reliability performances of the solder micro bump joints. However, which UBM structure/material for fine pitch solder micro bump joint presents the better reliability properties is not concluded yet until now. In this study, the effect of UBM structural/material on the reliability properties of lead-free solder micro interconnections with a pitch of 30μm was discussed. The chip-on-chip test vehicle with solder micro bump interconnections having a diameter of 18 μm was adopted to evaluate the effects of UBM structure/material. There were more than 3000 micro bumps with Sn2.5Ag solder material on both the silicon chip and carrier. In this study, three types of UBM were selected on the silicon carrier: they were single copper layer with a thickness of 8μm; the Cu/Ni layer with the thickness of 5μm/3μm and the Cu/Ni/Au layer with the thickness of 5μm/3μm/0.5μm. The UBM was electro-plated on the Al trace and then the Sn2.5Ag solder with a thickness of 5 μm was deposited. For the silicon carrier with the bump structure of Cu/Sn and Cu/Ni/Sn, the silicon test chip with solder micro bump of Cu/Sn was used for chip bonding. The test chip having the solder micro bump of Cu/Sn and Cu//Ni/Sn was used for bonding with the silicon carrier having the Cu/Ni/Au UBM. In chip stacking process, we adopted the fluxless thermocompression process for each type of micro joints. After chip bonding process, the fine gap between bonded chips was filled by capillary type of underfill. The influence of underfill on the reliability of solder micro bump interconnects with various combinations of UBM structures were estimated also. After the assembly process, temperature cycling test (TCT), high temperature storage (HTS) and electromigration test (EM) were performed on the chip-stacking module to assess the effect of UBM structure/material on the reliability of solder micro bump interconnections. The results of reliability test revealed that only Cu/Sn/Au/Ni/Cu micro joint could not pass the TCT and HTS of 1000 cycles. After reliability test, the Cu/Sn/Cu joints showed the evidently microstructural evolution while the Cu/Ni/Sn/Cu joints did not show apparent microstructure change among all the types of micro joints and still revealed the most contents of residual solder within the joint. On the other hand, the existence of Au layer upon the UBM caused the complicated interface reaction between solder and UBM, which presented a negative effect during long-term reliability performance. The reliability results also displayed that the introduction of underfill could apparently enhance the reliability of micro joint under mechanical evaluation. From the results of EM reliability test, all the types of the micro joints showed excellent electromigration resistance under current stress of 0.08A at an ambient temperature of 150°C irrespective of the types of UBM. This superior property was attributed to the microstructure change transformed from the solder joint to the IMC joint within the solder micro bump interconnections during electromigration test. All the results of reliability test illustrated that the selection of UBM structure/material well influenced the reliability performance of fine-pitch solder micro bump interconnections in 3D chip stacking. [ABSTRACT FROM PUBLISHER]

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments. [ABSTRACT FROM PUBLISHER]

In order to meet the demands of high-performance, high-speed, small form factor and multi-function integration in portable electronic products, the development of packaging technology now trends toward system-in-package (SiP) technology. Three-dimension (3D) integrated circuit technology provides a way to integrate complex micro systems through vertical interconnections among individual devices/chips. For the multi-chip stacking with fine gap and fine pitch solder micro bump interconnection, the dispensing of capillary underfill presents a major limitation in term of process time and process ability during assembly process. In this study, for realizing the multi-chip stacking, we developed a simplified assembly process by wafer-level underfill (WLUF). The WLUF film was laminated on 8” chip wafer with a thickness of 50µm. The chosen solder micro bump structure was Cu/Ni/Sn2.5Ag with a pitch of 30µm. After wafer dicing, the chip with WLUF was assembled on the substrate chip having the same micro bump structure. The optimized bonding parameters in such assembly process were also determined. The experimental results revealed that a robust joining and no voids formed between bonding interface could be achieved by this simplified assembly process. The results of reliability test showed that all samples could pass LV-3 pre-condition test. The failure percentage was about 10% under 1000 cycles of TCT where the failure mode was the cracks of micro joints and Al pad. The failure percentage was about 52% under 1000 hours of THST where the failure mode was crack of micro joints. All samples could pass the Un-biased HAST test. We also evaluated the feasibility of multi-thin-chip stacking by WLUF film. The experimental results showed that the first-layer micro joints raised 2% increase in contact resistance and the thickness of IMC layer increased 1µm thick only after four-layer chip stacking process. These experimental results displayed that the WLUF material exhibited a highly applied potential for multi-chip assembly process. [ABSTRACT FROM PUBLISHER]