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In this study, electrical measurements on ferroelectric random-access memory by prior x-ray irradiation are conducted. Compared with an unirradiated device, parameters such as current leakage and remnant polarization of the irradiated device were unexpectedly improved. Besides, better reliabilities including the number of endurance times and retention time have also been demonstrated. To clarify the underlying physical mechanism, the electrical properties are analyzed. The current–voltage curve (I–V) implies a change in the grain size in the ferroelectric layer (FL), and the capacitance–voltage curve (C – V) profile indicates that the FL undergoes a phase change during irradiation. Finally, according to the electrical results, a physical model is proposed as an explanation. [ABSTRACT FROM AUTHOR]

Phalaenopsis, an essential flower for export, is significantly affected by fusarium wilt, which impacts its export quality. Hyperspectral imaging technology offers the potential to detect fusarium wilt on Phalaenopsis. The goal of this study was to establish an automated platform for the rapid detection of fusarium wilt on Phalaenopsis. In this research, the automatic target generation process (ATGP) method was employed to identify outliers in the hyperspectral spectrum. Subsequently, the Spectral Angle Mapper (SAM) method was utilized to detect signals similar to the outliers. To suppress background noise and extract the region of interest (ROI), the Constrained Energy Minimization (CEM) method was implemented. For ROI classification and detection, a deep neural network (DNN), a support vector machine (SVM), and a Random Forest Classifier (RFC) were employed. Model performance was evaluated using three-dimensional receiver operating characteristics (3D ROC), and the automated identification system was integrated into hyperspectrometers. The proposed system achieved an accuracy of 95.77% with a total detection time of 3380 ms ± 86.36 ms, proving to be a practical and effective tool for detecting fusarium wilt on Phalaenopsis in the industry. [ABSTRACT FROM AUTHOR]

To investigate the driving safety of vehicles travelling on bridges which cross the sea in cold regions, this study presented a dynamic analysis framework for a vehicle–bridge–soil interactive system subjected to stochastic ice loads. Time histories of the stochastic ice loading based on real ice loading spectrum were obtained to consider them as external forces inputs to the vehicle–bridge–soil interaction model. Dynamic responses of a five-span continuous box-girder bridge seated on pile-type foundations under twelve 12-DOF truck vehicles moving are investigated. These numerical analyses revealed that both the bridge and vehicle vertical responses were little affected by lateral ice loads, although their lateral responses were dominated by ice loads. For vehicle driving safety, the front axle tires were more prone to sideslip accidents than rear axle tires were: higher vehicle speed, larger ice loading magnitude, and more slippery pavement adversely affected driving safety. Quantitative analysis was also done using the present dynamic analysis framework. In the worst case studied herein, the front axle tires approached sideslip status, with only 5 kN sideslip force resistance. [ABSTRACT FROM AUTHOR]

A method of using non‐volatile and fast ferroelectric field‐effect transistor (FeFET) devices to realize Boolean logic is proposed. First, the internal states are initialized. Then, the gate and body function as input terminals, which are used to write the states of the device, based on the voltage. Finally, the output signals can be easily read through the drain current. Of the 10 Institute of Electrical and Electronics Engineers (IEEE) standard logic gates, eight can be implemented using the proposed operation method alone and by following the definitions listed herein. Thus, to enable FeFET devices to act as functional logic gates, a simple operating method is proposed, providing substantial contributions to the development of computing in memory. The experimental results provide evidence of the efficacy of this method. [ABSTRACT FROM AUTHOR]

This investigation rationalizes the impact of oxide particles on the melt pool and subsequent formation of microstructure in superalloy Inconel 718 (Alloy 718) processed by laser powder bed fusion (L-PBF). A mixture of Alloy 718 powder with 0.2 wt pct of CoAl2O4 was processed without scan rotation. It was found that the physical presence of oxides appeared to increase the degree of melt pool penetration by inhibiting the heat transfer. Without favorable thermal conditions to trigger heterogeneous nucleation, a more noticeable tendency to form columnar grains was characterized in samples with CoAl2O4. It is believed that the presence of oxide particles in the melt pool contributed to decreasing the cooling rates during solidification and retarded the columnar-to-equiaxed transition. A comparatively deeper degree of melt pool penetration also enhanced the relative density of samples with CoAl2O4. Despite the occurrence of the balling phenomenon, the reduced Marangoni convection also contributed to less micro-humping and better continuity of the melt tracks that decreased the surface roughness by at least 16.7 pct. The addition of CoAl2O4 to the powder feedstock significantly impacted the processing window of L-PBF processed Alloy 718 and may potentially be used as a means to engineer the microstructure. [ABSTRACT FROM AUTHOR]

In this study, the threshold voltage (VT) degradation mechanism for a hot electron stress (HES) under semi-ON state conditions in AlGaN/GaN high electron mobility transistors is analyzed. The drain current versus gate voltage (ID–VG) characteristic curves indicate that VT shifts in the positive direction after the stress. However, an abnormal phenomenon that VT continuously shifts in the positive direction even after recovery is observed. A result comparison of a negative bias stress (NBS) experiment indicates that a hole recombination in pre-existing buffer defects is crucial. Therefore, a complete model of VT degradation mechanism is proposed. Moreover, the proposed model is confirmed through an illumination experiment and a Silvaco simulation. [ABSTRACT FROM AUTHOR]

As a transmitter power amplifier (PA), the electrical output characteristics of gallium nitride (GaN) high electron mobility transistors (HEMTs) are closely related to the drain current versus drain voltage (${I}_{d}$ – ${V}_{d}$) characteristics. Any abnormalities in the ${I}_{d}$ – ${V}_{d}$ characteristics will seriously affect device performance. Therefore, many groups have investigated the kink effect of GaN HEMTs. One of the commonly used measurement methods of the kink effect is the ${I}_{d}$ – ${V}_{d}$ forward and reverse sweep. In this study, we used the same method for Al2O3/Si3N4–AlGaN/GaN metal–insulator–semiconductor HEMT (MIS HEMT) devices. We found that not only did the kink effect occurred but ${I}_{d}$ also increased abnormally during the reverse sweep and after a series of electrical measurements. At the end of the forward sweep, impact ionization caused by a high ${V}_{d}$ generated electron–hole pairs and some holes accumulated under the gate region, which caused the negative shift of the threshold voltage (${V}_{\text{Th}}$), leading to an abnormal increase in ${I}_{d}$ during the reverse sweep. [ABSTRACT FROM AUTHOR]

This study investigates the recovery behavior of GaN high-electron mobility transistors on SiC substrates under different hot-carrier stress conditions. The threshold voltage shifts positively due to hot electron trapping at the buffer layer under hot-carrier stress. However, the recovery between semi-on (Vt < VG < 0 V) hot-carrier stress and on-state (VG > 0 V) carrier stress is significantly different. This phenomenon is systematically discussed in terms of the applied gate voltage under stress condition, which affects the occupation of the surface donor states. After applying a semi-on hot-carrier stress, the threshold voltage continues to shift positively after relaxing the applied voltage. In contrast, the threshold voltage exponentially recovers after applying an on-state hot-carrier stress. Silvaco technology computer aided design (TCAD) simulation was performed to verify the effect of the surface donor state on the threshold voltages. Since switching between on-state and off-state in RF-applications includes both conditions, we suggest that the surface donor states are crucial to determine the failure of devices. [ABSTRACT FROM AUTHOR]

This study investigates the properties of a onetransistor- one-capacitor (1T1C) device that includes a transistor and ferroelectric random access memory (FeRAM) at the nanoscale. The hysteresis characteristics are presented. A simultaneous measurement of writing and reading was used. A difference was observed between the forward and reverse transconductance (gm) −VG curves, and the reason can be explained by the relationship between the operating voltage and coercive voltages. According to the relationship between gm and polarization, the polarization signal can be obtained using gm at the nano-scale. The remnant polarization of the 1T1C device per unit ferroelectric-layer area was confirmed by the polarization value of FeRAM via the Positive Up Negative Down method. Finally, the P–V loops obtained using gm values with different measurement ranges are also reported. [ABSTRACT FROM AUTHOR]

This work investigates the effect of X-ray accelerating voltage (Vacc) on the structural repair of HfZrOx ferroelectric random-access memory. We found that X-rays are able to break the molecular bonds due to missing electrons, thereby repairing the material structure. To further understand the influence of X-ray Vacc on structural repair, we conducted different Vacc conditions, with results showing that there is only a small improvement under high Vacc. However, the improvement is much clearer under low Vacc. To illuminate these results, we propose a physical model which is based on different X-ray energies that will have different energy penetration capacities. [ABSTRACT FROM AUTHOR]

This study compares the capacitance–voltage (C–V) characteristics in silicon–germanium (SiGe) metal-oxide-semiconductor capacitances with and without a silicon oxide capping layer. The SiGe channel with the silicon oxide capping layer exhibits an improved C–V property at room temperature but has an abnormal shift and depression at low temperature (77 K). We determined that the threshold voltage shift was induced by the Fermi-level when ambient temperature was changed. The additional silicon capping layer was responsible for introducing defects resulting in depression and hump in the C–V measurements. Such a phenomenon is mainly caused by the different distribution of defects, which was established by modifying the alternating current pulse amplitude during the C–V measurement. [ABSTRACT FROM AUTHOR]

2D semiconductor field‐effect transistors (2D FETs) have emerged as a promising candidate for beyond‐silicon electronics applications. However, its device performance has often been limited by the metal‐2D semiconductor contact, and the non‐negligible contact resistance (RSD) not only deteriorates the on‐state current but also hinders the direct characterization of the intrinsic properties of 2D semiconductors (e.g., intrinsic charge carrier mobility, μint). Therefore, a proper extraction technique that can independently characterize the metal‐2D semiconductor contact behavior and the intrinsic properties of a 2D semiconducting layer is highly desired. In this study, a universal yet simple method is developed to accurately extract the critical parameters in 2D FETs, including characteristic temperature (To), threshold voltage (VT), RSD, and μint. The practicability of this method is extensively explored by characterizing the temperature‐dependent carrier transport behavior and the strain‐induced band structure modification in 2D semiconductors. Technology computer aided design simulation is subsequently employed to verify the precision of RSD extraction. Furthermore, the universality of the proposed method is validated by successfully implementing the extraction to various 2D semiconductors, including black phosphorus, indium selenide, molybdenum disulfide, rhenium disulfide, and tungsten disulfide with top‐ and bottom‐gated configurations. [ABSTRACT FROM AUTHOR]

In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the HCD under different gate voltages ($\text{V}_{\text {G}}$) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as $\text{V}_{\text {G}}$ increased, the HCD mechanism of the p- FinFET changed from electron–electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage ($\text{V}_{\text {T}}$) shift was observed for the n- FinFET. When $\text{V}_{\text {G}}$ increased to $\text{V}_{\text {T}}+1.2$ V for the n- FinFET and to $\text{V}_{\text {T}} -{0.8}$ V for the p- FinFET, $\Delta \text{V}_{\text {T}}$ began to increase rapidly under hot carrier stress. The distributions of $\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}}$ - ${I}_{D}$ for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as $\text{V}_{\text {G}}$ increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower $\text{V}_{\text {G}}$ value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET. [ABSTRACT FROM AUTHOR]

The HfZrOx (HZO) ferroelectric material is a promising material for ferroelectric memory and is compatible with the semiconductor process for ferroelectric random access memory (FeRAM) and negative capacitance field effect transistor. However, defects often exist in the grain boundary to influence the performance or reliability of devices. In addition, uniformity between devices must be considered when they are mass-produced. Therefore, the grain size will become important in determining the performance and reliability. In this study, we use electrical measurements of current–voltage, capacitance–voltage, and polarization–voltage measurements to test high- and low-temperature deposition devices, with a transmission electron microscope (TEM) image to confirm the grain size. Finally, we propose a model to explain the phenomenon and provide a method to obtain better ferroelectric memory. [ABSTRACT FROM AUTHOR]