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In this article, the proposed monolithic gallium nitride (GaN)-based driver uses the diode-emulated technique to reduce reverse conduction through a meta-stable fast (MSF) comparator with sub-0.2-ns deadtime. In addition, an active bootstrap controller with a fast discharge loop is used to reduce parasitic effects to improve the driving capability, thereby increasing the switching frequency. Furthermore, the proposed gate driver with dual $dv/dt$ control can reduce the gate-ringing during turn-on/turn-off. Experimental results show that the GaN-based monolithic driver can achieve an operating frequency of 50 MHz and a slew rate of 120 V/ns. At 50 MHz, the conversion of 48-to-5 V can achieve a peak efficiency of 95.4% at the load current of 3.5 A. [ABSTRACT FROM AUTHOR]

This article proposes an envelope tracking supply modulator (ETSM) that recycles the originally wasted energy in the linear amplifier (LA) to generate negative voltage $V_{\mathrm {NEG}}$ and achieve fast down tracking. With the insertion of $V_{\mathrm {NEG}}$ , the negative slope of $I_{\mathrm {BUCK}}$ becomes 25% larger. $V_{\mathrm {NEG}}$ is also used to boost the input voltage of buck converter from 2 $V_{\mathrm {BAT}}$ to 2.6 $V_{\mathrm {BAT}}$ and raise the positive slope of $I_{\mathrm {BUCK}}$ by 93%, which improves the transient response of buck converter and decreases $\vert I_{\mathrm {LA}}\vert $ by 37%. With energy recycling and high-bandwidth LA replica, ETSM supports 150-MHz 5G new radio (5G NR) application and achieves 89.7% efficiency when output power is 3.7 W. In addition, the proposed differential feedforward technique controls the operation of energy recycling precisely with the calibration logic. [ABSTRACT FROM AUTHOR]

This article presents a one-stage buck converter with an accurate nanosecond ON-time ($T_{\mathrm{\scriptscriptstyle ON}}$) control for 48–1-V direct conversion for automotive applications. In order to overcome the low duty cycle from 48 to 1 V, the proposed high-voltage storage and low-voltage boost (HSLB) bootstrap circuit can reduce the level shifter delay to close to zero and the bootstrap delay to less than 2 ns. In addition, the early comparison $T_{\mathrm{\scriptscriptstyle ON}}$ generator can reduce the comparator delay ($T_{d\_{}{\mathrm{ comp}}}$) to close to zero at steady state to achieve precise nanosecond pulse $T_{\mathrm{\scriptscriptstyle ON}}$. On the other hand, $T_{d\_{}{\mathrm{ comp}}}$ can be quickly extended to increase $T_{\mathrm{\scriptscriptstyle ON}}$ by 540% to achieve fast transient with the recovery time of 3 $\mu \text{s}$ , in case load changes from 200 mA to 1 A. Based on the precise nanosecond $T_{\mathrm{\scriptscriptstyle ON}}$ , the OFF-time is extended by the load-dependent current limiting OFF-time modulation for improving light-load efficiency. Experimental results show that the peak efficiency reaches 96.5%, 95.1%, and 92.8% when $V_{\mathrm {IN}}$ is 12, 24, and 48 V, respectively, for $V_{\mathrm {OUT}} = 1$ V. [ABSTRACT FROM AUTHOR]

Without the Fluorinert solution and proper pad design, the high–voltage (HV) transistor used during the DC breakdown voltage (Vbk) measurement might be damaged by the partial discharge (PD) in the air if its Vbk is close to one thousand volts or more. From the waveform measurement, the PD in the air occurred at 650 V HV GaN HEMTs during the Vbk measurement, it is ignited by the unipolar arc, and it is not ignited by the avalanche breakdown. This is based on the fact that the current falls below zero ampere to become a negative current, and the voltage rises so that it is higher than the setting voltage of the DC meter at the onset of the PD, thus corresponding with the electrons, leaving the plasma to cathode, and enabling a build–in potential to exist in the plasma. Then, the PD ignites because the current starts to rise in order to allow for a positive spike current; the voltage level subsequently falls and a lower voltage reading is obtained. [ABSTRACT FROM AUTHOR]

This article proposes a single-inductor multi-output converter implemented in $0.153 \mu{\mathrm {m}}$ CMOS process, including the adaptive switchable continuous conduction mode (CCM) and discontinuous conduction mode (DCM) (ASCD) technique, and a five-input crosstalk reduction error amplifier (CREA) to minimize the cross regulation to 0.03 mV/mA and achieve load capability up to 3 W. At ultra-light loads, the proposed ultralow power (ULP) mode is applied to reach 185 nA quiescent current and enhance light load power efficiency. Moreover, the peak efficiency is as high as 94.3% with a chip area of $1.2 \times 1.7$ mm2. [ABSTRACT FROM AUTHOR]

A boost converter with buck-store and boost-restore (BSBR) technique fabricated by 0.25 [micro]m CMOS BCD process can provide different supply voltages to drive series red, green, and blue LEDs in sequence for reducing the power consumption on the constant current generator. The proposed technique not only stores and restores extra energy during the transient time of the reference tracking response to improve the efficiency but also enhances the reference tracking response to greatly reduce load transition time. Experimental results show that the period of reference tracking response can be improved. When the load current is 100 mA, the periods of reference down-tracking and up-tracking are smaller than 10 and 20 [micro]s, respectively. Furthermore, this technique can also provide a regulated voltage to drive the subblock implemented in the liquid crystal display system. The maximum efficiency of charge recycling is up to 94%, and the maximum efficiency of this boost converter is 94.5%. Experimental results demonstrate fast and efficient reference tracking performance is achieved by the proposed BSBR technique. Index Terms--Charge recycling, dc--dc converter, field color sequential (FCS), reference tracking.

This paper presents a new adaptive window control (AWC) technique to adjust the hysteresis window to reduce the output ripple at heavy loads and keep the switching frequency higher than the acoustic frequency at light loads. Therefore, the driving capability and the power conversion efficiency of the hysteresis converter are improved at heavy loads. Besides, a new class AB current sensing circuit is also proposed to provide fast and accurate current sensing signal for achieving fast hysteresis window adjustment. Experimental results show that the proposed AWC technique not only reduces the output ripple smaller than 12 mV when load current is 800 mA to improve the power conversion efficiency but also keeps the switching frequency higher than acoustic frequency at light loads to avoid undesired noise. Index Terms--Adaptive window control, hysteresis converter, output ripple.

Power management is implemented in a multiple-input--single-output system in this paper. Actually, the design of the switching loss calculation circuit in a dynamic droop system (DDS) can decide the optimum driving solution according to the loading condition, i.e., more than one input source is disabled to reduce the switching loss at light loads. On the other hand, multiple-input sources are preferred to reduce the conduction loss at heavy loads. In other words, DDS with power management can achieve low drop output voltage and high efficiency over a wide load range. The positive/negative-compensated technique enhances the performance of the output voltage stability. Experimental results show that efficiency can be improved approximately 12% at light loads when two input sources are regulated at the switching frequency equal to 5 MHz. Simultaneously, good current sharing is also guaranteed. Index Terms--Dynamic droop, multiple input, positive/negative compensated (PNC), single output, switching loss calculation (SLC).

This paper proposes a low-ripple and dual-phase charge pump circuit regulated by switched-capacitor-based bandgap reference. Due to design of a buffer stage, a system can have better bandwidth and phase margin, and thus, the transient response and driving capability can be improved. Besides, the dual-phase control can reduce the output voltage ripple by means of only one closed-loop regulation in order to improve the power conversion efficiency. Besides, the proposed automatic body switching (ABS) circuit can efficiently drive the bulk of the power p-type MOSFETs to avoid leakage and potential latch-up. Usually, the regulated charge pump circuit needs a bandgap reference circuit to provide a temperature-independent reference voltage. The switched-capacitor-based bandgap reference circuit is utilized to regulate the output voltage. This chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 [micro]m 3.3 V/5 V 2P4M CMOS technology. The input voltage range varies from 2.9 to 5.5 V, and the output voltage is regulated at 5 V. Experimental results demonstrate that the charge pump can provide 48 mA maximum load current without any oscillation problems. Index Terms--Bandgap reference, charge pump, dual-phase power stage, fast transient response, output ripple, system-on-chip (SoC).

An adaptive reference control (ARC) technique is proposed for minimizing overshoot/undershoot voltage and settling time of low-dropout regulators. Linear operation provided by the ARC technique can dynamically and smoothly adjust the reference voltage so as to increase the slew rate of error amplifier thus forcing the output voltage back to its steady-state value rapidly. The amount of transient revision is proportional to transient state output voltage variation and load condition. In addition, a dynamic push-pull technique is used to enhance transient response. Experimental results demonstrate that the undershoot voltage, settling time, and load regulation are improved by 31%, 68.5 %, and 70 %, respectively, when load current changes between 1 and 100 mA. Index Terms--Analog ICs, CMOS analog ICs, dc-dc power conversion, MOSFET ICs.

For automobile applications, a high-speed switching 48-to-5 V dc–dc buck converter is implemented in the 0.5- $\mu \text{m}$ CMOS and 0.5- $\mu \text{m}$ gallium nitride (GaN)-on-Si processes. This proposed converter includes a pre-charge tracking technique, a temperature-dependent controlled gate driver, and an adaptive relaxation gate drive control technique. The measurement results of this article show that the efficiency can be increased by about 10.3% and can ensure the driving current capacity of enhance GaN (E-GaN). The built-in local negative feedback loop improves the reliability and reduces $R_{\mathrm{\scriptscriptstyle ON}}$ by 21% to reach the peak efficiency as high as 95.4%. [ABSTRACT FROM AUTHOR]

This article presents a three-switch (3S) boost converter with hysteresis current control applied in MiniLED panels. It uses only three power switches to achieve high conversion ratio (=7.5) and low inductor current (20% lower than conventional boost converters). Meanwhile, the charging time of the flying capacitor will increase as the duty cycle increases. It enables the proposed 3S boost converter to have a high drive current (=1.2 A). In addition, the right half-plane (RHP) zero of the proposed topology is related to the switching frequency. By dynamically adjusting the position of RHP zero during transients, the recovery time and output voltage drop can be reduced at the same time. When the load increases from 120 mA to 1.2 A, the recovery time can be accelerated to 42 $\mu \text{s}$ , and the maximum efficiency can reach 97.4%. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive pole-zero position (APZP) technique to achieve excellent transient response of dc-dc converters. The APZP technique triggers the two-step nonlinear control mechanism to speed up the transient response at the beginning of load variations. Before the output voltage is regulated back to its voltage level, the APZP technique merely functions as a linear control method to regulate output voltage in order to ensure the stability of the system. Fast transient response time, low output ripples, and stable transient operation are achieved at the same time by the proposed APZP technique. Experimental results in the UMC 0.18-[micro]m process show that the transient undershoot/overshoot voltage and the recovery time do not exceed 48 mV and 10 [micro]s, respectively. Compared with conventional design without any fast transient technique, the performances of overshoot voltage and recovery time are enhanced by 37.2% and 77.8%. With the APZP technique, the performance of dc-dc converters is improved significantly. Index Terms--Adaptive frequency control, current-mode dc-dc converter, fast transient response, load transient, on-chip compensation.

This paper proposes an advanced Q-reduction technique of pole-splitting compensations for low dropout (LDO) regulator. The output pole is load dependent and may cause the scenario of complex poles when load current changes. LDO regulators may oscillate because high-Q incurs the less gain and phase margins. The reasons of causing complex poles depend on the design methodology. For the design of capacitor-free LDO regulator, high-Q issue happens when load current changes from heavy to light. Recent literature provides a method to alleviate the high-Q problem. However, large dropout voltage in case of suddenly large loads forces designers to include a small load capacitor as an indispensable component for supplying system-on-chip (SoC) systems. Different to the case of capacitor-free LDO regulators, high-Q issue happens when load current changes from light to heavy. According to our proposed power MOSFET array, the high-Q problem can be alleviated and prevent LDO regulators from oscillating when load changes. Experimental results promise the stability and show the improvement of load and line regulations. Index Terms--Capacitor-free, complex pole, low-dropout regulator (LDO), power MOSFET array, Q-reduction.

Single-ended and two-ended bidirectional capacitor multipliers for providing on-chip compensation, soft-start, and fast transient mechanisms are proposed in this paper. The bidirectional current mode capacitor multiplier technique can effectively move the crossover frequency toward to the origin in the start-up period for a smoothly rising of the output voltage. Besides, the small time constant is set by the fast transient control circuit in order to get a higher crossover frequency. Thus, the output voltage can be regulated to its stable value as fast as it can when large load current changes. A test chip fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-[micro]m process verifies the correctness of the bidirectional current mode capacitor multiplier technique. Experimental results demonstrate the transient speed by our proposed technique is faster than that by conventional control by about 2 times, and there is only about 76% dropout voltage of the conventional design with off-chip compensation. The proposed circuits consume more quiescent current about 10 [micro]A in single-ended capacitor multiplier and 20 [micro]A in two-ended capacitor multiplier. With the proposed bidirectional current mode capacitor multiplier technique, the performance of dc-dc converters is improved significantly and the external pins and footprint area are minimized. Index Terms--Capacitor multiplier, compensator, current mode, dc-dc converter, on-chip compensation.

In this article, a monolithically integrated driver fabricated by 12-V depletion mode gallium nitride (dGaN) and enhanced mode GaN (eGaN) driver is proposed. The proposed driver features an internal temperature-compensated (T-compensated) controller to drive an integrated 650-V eGaN power switch. Due to T-compensated characteristics, a slew-rate enhancement driver can be well-controlled by the fast turn-on (FTO) technique which is supplied by an on-chip regulator with reference voltage circuit. Therefore, the Miller plateau voltage can be tracked correctly by the proposed controller so that the switching frequency can be raised up to 50 MHz and the $\textit {dV}_{\mathrm {DS}}$ / dt slew rate can reach 118.3 V/ns for high efficiency and high switching operation. [ABSTRACT FROM AUTHOR]

This article proposes a dual voltage/current (V/C) inductance controller, which has good impedance tracking capability without any high-voltage stress problems. Besides, the proposed dual-mode phase-locked loop (D-PLL) technique can detect the phase difference between voltage and current of the antenna by fast tracking PLL and the accuracy-improved PLL for inductive and capacitive loads, thereby improving efficiency. Therefore, the 5G small base station on the receiver side (RX) can receive 27.8 W of power with 50% efficiency when the wall thickness to the transmitter side (TX) is 25.2 cm. In the case where the distance between TX and RX is close to zero, 50 W higher power with 90% efficiency can be achieved. Accordingly, the efficiency of resistive and inductive loads can be increased by 13% and 41%, respectively. [ABSTRACT FROM AUTHOR]

This article proposes a supply modulator (SM) that uses high switching frequency gallium-nitride (GaN) devices to achieve a four-phase fast step-down converter for the fast-tracking ability of the envelope tracking (ET). The ET signal is reshaped to generate an average power tracking (APT)-based signal to control the size of GaN switches to further increase light-load efficiency due to reduced switching loss. Moreover, a high-bandwidth and low-loss linear amplifier (LA) is used to supply the power amplifier (PA) to sufficiently provide fast-tracking speed for 5th generation (5G) NR ET. At a power of 3.5 W for 5G mobile phones, the peak efficiency that is tested with NR −130 MHz in the ET mode is as high as 85.7% over a wide load range. [ABSTRACT FROM AUTHOR]

Compared to Si FETs, when the main GaN FET is in full zero voltage switching condition, maximum switching loss reduction can be achieved. Therefore, in this article, an active clamp flyback converter with GaN devices that implements fast ZVS by using the proposed dynamic resonant period control (DRPC) technique can reduce large transformer leakage inductance energy loss on the active resonant circuit. As the loading changes, the DRPC technique can dynamically adjust the on-time in auxiliary switch to prevent large voltage stress on the components in the primary side. In full load condition, the leakage energy loss can be reduced, thereby transferring more energy to the secondary side with maximum efficiency up to 94%. [ABSTRACT FROM AUTHOR]

The proposed digital low-dropout regulator uses nonlinear switching control (NLSC) technique to suppress voltage ripple to less than 6 mV when the switching noise voltage of a switching regulator operating in a power-saving mode is greater than 50 mV. In addition, the NLSC technique improves the current efficiency by reducing the quiescent current to less than 10 μA and reduces the switching power loss through variable switching frequency control. With a load step of 1–20 mA, the transient response time is 1.3 μs and the peak current efficiency is 99.8% at heavy loads. [ABSTRACT FROM AUTHOR]

For high-security Internet-of-Everything (IoE) devices, a true random number (TRN)-based pseudohysteresis controller (PHC) is proposed to avoid both power side-channel attack (PSCA) and power injection attack (PIA) and reduce electromagnetic interference (EMI) without degrading performance of transient response and regulation. In addition, the TRN-based PHC uses an enhanced security randomizer to correctly generate a random number (RN) independent of the input power at the PSCA and PIA and converts the RN into a hysteresis window that constitutes the true random modulation switching frequency. Therefore, the TRN-based PHC ensures proper spread spectrum and low EMI. In addition, fast transient response is maintained due to inherent hysteresis control. Experimental results show that peak EMI noise is reduced from 89.72 to 54.32 dBμV and meets the specification of EN 55032 Class B even under the PIA interference up to 1 V. Furthermore, in case of 0.2 A-to-0.8 A load step, the method achieves a recovery time of 7.3 μs and an output voltage drop of 53 mV at a switching frequency of approximately 1 MHz, and the peak efficiency is 92.4%. [ABSTRACT FROM AUTHOR]

This paper presents a modified negator-based switched-capacitor (NSC) dc–dc converter to achieve fine-grained voltage conversion ratios. Based on a concept of reconfiguring several 2:1 switched-capacitor (SC) converters in series and parallel at the last stage, the proposed asymmetrical shunt SC (ASSC) converter provides more controllable variables of forward gain and feedback gain to decide different power path interconnections and increase the available conversion ratios, with a little sacrifice of its slow switching limit output impedance. The switching loss of the bottom-plate parasitic capacitance in the ASSC converter is less than the switching loss of the NSC topology because the two moderate voltages instead of the power rail are fed to the last stage 2:1 SC unit and reduce the voltage swing. The bottom-plate swapping prototype further reduces the parasitic loss at high conversion ratios. To handle a large number of conversion ratios in closed-loop regulation, the ASSC converter uses the fast optimum ratio searching (FORS) technique, which evaluates the transient voltage drop to quickly search for target ratios and reduce the transient recovery time. A three-stage ASSC converter achieving 187 conversion ratios is fully integrated in the test chip, which is fabricated in 0.25-μm CMOS process with an active area of 7.14 mm2. Furthermore, 2389 conversion ratios can be derived in theory for a four-stage ASSC converter. The proposed reconfigurable SC converter provides an output voltage range of 0.4 to 2.8 V under no load conditions, and greater than 80% power efficiency at an output voltage level of 0.9 to 1.5 V over a load range of 3 to 9.5 mA. Due to the FORS technique, the measured transient recovery time is reduced from 7 to 1.5 μs in case of load current step of 7 mA. [ABSTRACT FROM AUTHOR]

State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1~1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100~300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer $ {\sigma }/ {\mu }$ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW. [ABSTRACT FROM AUTHOR]

Stacked mosfet structures made of low-voltage devices suffer from degraded transient response or large footprint when a capacitorless or dominant-pole compensated low-dropout (LDO) regulator biases the driver. Due to the self-stabilizing nature, the proposed stacked mosfet driver (SMD) technology effectively drives the power stage and greatly reduces the noise at the switching nodes for low cross regulation (CR) in a single-inductor dual-output (SIDO) converter. In addition, two inherent LDO regulators in SMD technology fully regulate the dual outputs with the advantage of low quiescent current at no-load conditions. The experimental results show that the test chip fabricated under the 0.25-μm process has low CR of 0.015 mV/mA and ultralow quiescent current of 5 μA under no-load conditions. [ABSTRACT FROM AUTHOR]

Constant-on-time (COT) control with an additional current feedback path in conventional buck converters can remove the need of large equivalent series resistance (ESR) at the output capacitor but it induces degraded output voltage regulation accuracy and slow transient response owing to opposite reaction between the output voltage and the additional current feedback information. Therefore, this paper proposes the pseudowave tracking (PWT) technique to reduce the load-dependent dc offset voltage of output load regulation while keeping the fast transient response similar to conventional COT buck converter with large ESR. The PWT technique further improves the transient response instantly by extending on-time and off-time periods during light-to-heavy and heavy-to-light load changes, respectively. The test chip fabricated in 28 nm CMOS process has demonstrated the improvement of offset voltage from 42 to 4 mV, while the transient response can be improved to 4 and 5 μs with load changes from 0.3 to 1.7 A and vice versa, respectively. [ABSTRACT FROM PUBLISHER]

The state-of-the-art topology of a single-inductor multiple-output light emission diode (LED) driver employs time-multiplexing (TM) control multiple parallel LED strings. The TM control technology provides large output current but the inductor current is separated to several parts and unable to be used simultaneously. The limitation of TM control also results in low dimming frequency and low color resolution. Thus, a single-inductor multiple-floating-output (SIMFO) LED driver with the average current correction (ACC) technique is proposed to solve these problems, so the inductor current is simultaneously utilized by every LED in series, with enhancement of luminous efficiency. Furthermore, the proposed ACC technique adaptively adjusts the average current to eliminate the current cross-regulation effect occurring in different dimming patterns, so each different color LED has its own dimming ratio. The test chip is fabricated in a 0.5-μm high voltage (HV) process with an active area of 15 mm2 , and experimental results show the proposed LED driver achieves 24-b color resolution with 12 W output power and maintains 96% high efficiency in the RGBW LED applications. [ABSTRACT FROM PUBLISHER]