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Silicon quantum dot spin qubits have great potential for application in large-scale quantum circuits as they share many similarities with conventional transistors that represent the prototypical example for scalable electronic platforms. However, for quantum dot formation and control, additional gates are required, which add to device complexity and, thus, hinder upscaling. Here, we meet this challenge by demonstrating the scalable integration of a multilayer gate stack in silicon quantum dot devices using self-alignment, which allows for ultra-small gate lengths and intrinsically perfect layer-to-layer alignment. We explore the prospects of these devices as hosts for hole spin qubits that benefit from electrically driven spin control via spin–orbit interaction. Therefore, we study hole transport through a double quantum dot and observe current rectification due to the Pauli spin blockade. The application of a small magnetic field leads to lifting of the spin blockade and reveals the presence of spin–orbit interaction. From the magnitude of a singlet-triplet anticrossing at a high magnetic field, we estimate a spin–orbit energy of ∼ 37 μ eV , which corresponds to a spin–orbit length of ∼ 48 nm. This work paves the way for scalable spin-based quantum circuits with fast, all-electrical qubit control. [ABSTRACT FROM AUTHOR]

In this letter we report on high-performance InGaAs FinFETs with optimized on-off trade-off. The InGaAs FinFETs are fabricated on silicon substrate using a CMOS-compatible replacement-metal-gate process. Excellent off-state performance is achieved by introducing source-drain spacers and doped extension regions. Extensions are fabricated using a digital etching process, a cycling etching technique that allows one to carefully control the position of the junction underneath the spacers. FinFETs with gate length of 13 nm show an on-current of 300 μA μm−1 at VDD = 0.5 V and fixed IOFF = 100 nA μm−1, the highest reported for ultra-scaled Si CMOS-compatible III–V FETs. [ABSTRACT FROM AUTHOR]

High-frequency InGaAs-On-Si MOSFETs with gate lengths down to 14 nm and a Si CMOS compatible fabrication flow are demonstrated. Record high combined $\text{f}_{\text {t}}$ and $\text{f}_{\text {max}}$ of 370 and 310 GHz, respectively, for III-V MOSFETs on Si is achieved. The key features include an InP/10 nm In0.75Ga0.25As/InP quantum well in the channel, as well as, self-aligned 8 nm thick source and drain spacers together with source and drain extensions, which minimize the parasitic access resistances due to the spacers. The use of the quantum well is shown to increase the electron mobility by a factor of three, resulting in a significant increase of $\text{g}_{\text {m}}$ due to a reduction of defect scattering at the gate oxide interface. The InP barrier is also shown to suppress the effect of border traps, through a reduction of the $\text{g}_{\text {m}}$ frequency dispersion. [ABSTRACT FROM AUTHOR]

To develop a new generation of high-speed photonic modulators on silicon-technology-based photonics, new materials with large Pockels coefficients have been transferred to silicon substrates. Previous approaches focus on realizing stand-alone devices on dedicated silicon substrates, incompatible with the fabrication process in silicon foundries. In this work, we demonstrate monolithic integration of electro-optic modulators based on the Pockels effect in barium titanate (BTO) thin films into the back-end-of-line of a photonic integrated circuit (PIC) platform. Molecular wafer bonding allows fully PIC-compatible integration of BTO-based devices and is, as shown, scalable to 200 mm wafers. The PIC-integrated BTO Mach–Zehnder modulators outperform conventional Si photonic modulators in modulation efficiency, losses, and static tuning power. The devices show excellent VπL (0.2 Vcm) and VπLα (1.3 VdB), work at high speed (25 Gbps), and can be tuned at low-static power consumption (100 nW). Our concept demonstrates the possibility of monolithic integration of Pockels-based electro-optic modulators in advanced silicon photonic platforms. [ABSTRACT FROM AUTHOR]

CMOS-compatible III–V lasers integrated on silicon are a crucial step to reduce power consumption and cost for next-generation optical transceivers. Here, we demonstrate a concept to co-integrate III-V lasers into a CMOS Silicon Photonics platform, in which lasers, photonics, and electronic circuitry share the same back end of line. Based on a bonded III–V epitaxial layer stack, ultra-thin laser devices, optically pumped lasing and coupling to silicon are demonstrated. Furthermore, we present all building blocks for electrically pumped laser devices. [ABSTRACT FROM AUTHOR]

The development of integrated photonic circuits utilizing gallium phosphide requires a robust, scalable process for fabrication of GaP-on-insulator devices. Here, we present the first GaP photonic devices on SiO2. The process exploits direct wafer bonding of a GaP/AlxGa1-x P/GaP heterostructure onto a SiO2-on-Si wafer followed by the removal of the GaP substrate and the AlxGa1-xP stop layer. Photonic devices such as grating couplers, waveguides, and ring resonators are patterned by inductively coupled-plasma reactive-ion etching in the top GaP device layer. The peak coupling efficiency of the fabricated grating couplers is as high as −4.8 dB. Optical quality factors of 20 000 as well as second- and third-harmonic generation are observed with the ring resonators. Because the large bandgap of GaP provides for low two-photon absorption at telecommunication wavelengths, the high-yield fabrication of GaP-on-insulator photonic devices enabled by this work is especially interesting for applications in nanophotonics, where high quality factors or low mode volumes can produce high electric field intensities. The large bandgap also enables integrated photonic devices operating at visible wavelengths. [ABSTRACT FROM AUTHOR]

Ultrathin-body (UTB) III–V channel MOSFETs are known to suffer from the floating body effect which turns on a parasitic bipolar junction transistor (BJT) and increases the off-state leakage current. This paper presents a TCAD simulation study of UTB In0.53Ga0.47As n-channel MOSFETs with nanowire and planar device geometry, each with different gate lengths ( ${L}_{G}$ ) ranging from 13 to 300 nm. A single set of parameters results in good agreement with measured transfer characteristics of all six different device geometries. The impact of band-to-band tunneling (BTBT), trap-assisted tunneling (TAT), and the electrostatic effect of traps at the buried-Al2O3/InGaAs interface has been deconvoluted during the TCAD analysis. It is found that the turn-on of the parasitic BJT is mainly caused by the combined effect of BTBT at the channel–drain junction and TAT at the gate-oxide/drain overlap. Furthermore, it is revealed that traps at the buried-Al2O3/InGaAs act as a backgate and degrade the subthreshold swing of the planar MOSFETs. The off-state leakage due to the parasitic BJT could be minimized with the help of an oxide spacer between HfO2 and InGaAs drain and by introducing a dopant grading at the source–channel and the drain–channel interfaces. [ABSTRACT FROM AUTHOR]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

Ultrafast and highly efficient optical modulators that are based on the Pockels effect are key components of today's optical communication networks. For the next generation of photonic links, silicon photonic technology is used to establish a new wave of densely integrated optic components. However, this new technology cannot exploit the advantages of using the Pockels effect for optical switching for two reasons: First, silicon does not exhibit any Pockels effect, and second, attempts to combine nonlinear materials with silicon photonics have been cumbersome. Here, we demonstrate a path to integrate barium titanate thin films with strong Pockels coefficients into silicon photonic structures. We highlight various design options, discuss the actual fabrication process, and present experimental results of functional passive and active structures. Examples include couplers and interferometers, as well as active, electrically driven nonvolatilely tunable ring resonators with a tunability of 4 μW/nm. Our results represent a major advancement in the field of ultralow-power silicon photonic switches based on nonlinear oxides, and demonstrate the potential of novel applications based on the hybrid barium titanate–silicon photonic platform. [ABSTRACT FROM PUBLISHER]

We report CMOS-compatible n -channel InGaAs-on-insulator FinFETs obtained using a replacement metal gate fabrication flow. The fabricated devices feature 12-nm-thick SiNx spacers, a scaled high- k /metal gate (capacitance equivalent thickness of \sim 1.5 nm), raised source and drain doped to /cm3, and fin width scaled down to 15 nm. Very good control of short-channel effects is demonstrated down to a gate length of 50 nm with a minimum subthreshold swing of 92 mV/decade at V_{DS}=0.5 V and a drain-induced barrier lowering of 57 mV/V. An ON-state current ( I_{{\textit {ON}}}) of 156 \mu \textA/\mu \textm is also reported for a supply voltage of 0.5 V and a fixed OFF-state current of 100 nA/ \mu \textm . This ION value is the highest reported to date for CMOS-compatible InGaAs devices integrated on Si. [ABSTRACT FROM PUBLISHER]

Integration of magnetic impurities into semiconductor materials is an essential ingredient for the development of spintronic devices such as dilute magnetic semiconductors. While successful growth of ferromagnetic semiconductors was reported for III-V and II-VI compounds, efforts to build devices with silicon technology were hampered by segregation and clustering of magnetic impurities such as manganese (Mn). Here, we report on a surface-based integration of Mn atoms into a silicon host. Control of Mn diffusion and low-temperature silicon epitaxy lead to confined Mn δ-layers with low interface trap densities, potentially opening the door for a new class of spintronic devices in silicon. [ABSTRACT FROM AUTHOR]

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec. [ABSTRACT FROM AUTHOR]

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal⁻organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n⁺ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

We investigated during the first lithiation/delithiation process the electrochemical reaction mechanisms at the surface of 30 nm n-doped amorphous silicon (a-Si) thin film used as a negative model electrode for Li-ion batteries. Usage of thin film allowed us to accurately discern the different reaction mechanisms occurring at the surface by avoiding interference from carbon and binder components. The potential dependency of the evolution of the solid electrolyte interphase (SEI) and the reactions on the a-Si and on the copper current collector were elucidated by coupling galvanostatic cycling with postmortem X-ray photoemission spectroscopy and scanning electron microscopy analyses. Our approach revealed the clear reversibility of lithiation/delithiation in the a-Si and native SiO 2 layers; such a reaction for SiO 2 has not been previously detected and was considered to be an irreversible process. Quantitative and qualitative analyses of the potential-dependent surface evolution revealed the decomposition products of both the salt (LiPF 6 ) and solvent (dimethyl carbonate/ethylene carbonate), giving insight into the complex SEI formation mechanism on the a-Si film but also underlining the strong influence of "inert" materials such as the role of the current collector in the irreversible charge loss. A model mechanism describing the evolutionary complexity of the a-Si surface during the first galvanostatic cycle is proposed and discussed.