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11 results on '"Diana Goehringer"'

1. AITIA: Embedded AI Techniques for Industrial Applications

Author

Bruno da Silva, Jurgen Vandendriessche, Marcelo Brandalero, Abdellah Touhafi, Laurens Le Jeune, Diana Goehringer, Toon Goedemé, Mitko Veleski, Michael Hübner, Lancelot Charles Lhoest, Hector Gerardo Munoz Hernandez, Nele Mentens, Muhammad Ali, Multidimensional signal processing and communication, Electronics and Informatics, Faculty of Engineering, and Engineering Technology

Subjects
driver-assistance systems, Industry 4.0, Computer science, Advanced driver assistance systems, artificial intelligence, Machine Learning, Intelligent sensor, smart sensors, Systems engineering, Use case, embedded systems, Network intrusion detection, industry 4.0, network intrusion detection
Abstract

Motivated by an increasing interest from startups in embedded Artificial Intelligence (AI) and by their limited expertise, the AITIA Project targets the development of embedded AI techniques for industrial applications. This extended abstract presents the motivation and the solutions being developed towards four use cases: smart sensors, network intrusion detection, driver-assistance systems, and Industry 4.0.

Published
2021

2. Prospects of Robots in Assisted Living Environment

Author

Ariel Podlubne, Sergio Andres Pertuz Mendez, Christos S. Antonopoulos, Safdar Mahmood, Michael Hübner, Kwame Owusu Ampadu, Diana Goehringer, Christos Panagiotou, Georgios Keramidas, Konstantinos Antonopoulos, and Nikolaos S. Voros

Subjects
TK7800-8360, Computer Networks and Communications, Computer science, pandemics, artificial intelligence (AI), rehabilitation, Human–computer interaction, Health care, Elderly people, Electrical and Electronic Engineering, Assisted living, business.industry, machine learning (ML), healthcare, Research opportunities, assisted living environment (ALE), human-machine interaction (HMI), social-distancing, Intelligent robots, Hardware and Architecture, Control and Systems Engineering, Signal Processing, Robot, robots, embedded systems, Electronics, business
Abstract

From caretaking activities for elderly people to being assistive in healthcare setup, mobile and non-mobile robots have the potential to be highly applicable and serviceable. The ongoing pandemic has shown that human-to-human contact in healthcare institutions and senior homes must be limited. In this scenario, elderlies and immunocompromised individuals must be exclusively protected. Robots are a promising way to overcome this problem in assisted living environments. In addition, the advent of AI and machine learning will pave a way for intelligent robots with cognitive abilities, while enabling them to be more aware of their surroundings. In this paper, we discuss the general perspectives, potential research opportunities, and challenges arising in the area of robots in assisted living environments and present our research work pertaining to certain application scenarios, i.e., robots in rehabilitation and robots in hospital environments and pandemics, which, in turn, exhibits the growing prospects and interdisciplinary nature of the field of robots in assisted living environment.

Published
2021
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3. Double-Layer Energy Efficient Synchronous-Asynchronous Circuit-Switched NoC

Author

Klaus Hofmann, Sandy A. Wasif, Diana Goehringer, Mohamed A. Abd El Ghany, and Salma Hesham

Subjects
Power gating, TK7800-8360, Computer Networks and Communications, Computer science, 02 engineering and technology, Data access layer, Dark silicon, 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Circuit switching, dark silicon, business.industry, circuit switching, 020208 electrical & electronic engineering, power consumption, asynchronous designs, 020202 computer hardware & architecture, Hardware and Architecture, Control and Systems Engineering, Asynchronous communication, Embedded system, Signal Processing, Dynamic demand, Scalability, power gating, Electronics, business, NoC, Asynchronous circuit
Abstract

A network-on-chip (NoC) offers high performance, flexibility and scalability in communication infrastructure within multi-core platforms. However, NoCs contribute significantly to the overall system’s power consumption. The double-layer energy efficient synchronous-asynchronous circuit-switched NoC (CS-NoC) is proposed to enhance the power utilization. To reduce the dynamic power consumption, single-rail asynchronous protocols are utilized. The two-phase and four-phase encoding algorithms are analyzed to determine the most efficient technique. For the data layer, the two asynchronous protocols reduced the power consumption by 80%, with an increase in latency when compared with the fully synchronous protocol. However, the two-phase single-rail protocol had better performance compared with the four-phase protocol by 38%, with the same power consumption and a slight increase in area of 5%. Based on this conducted analysis, the asynchronous two-phase layer had significant power reduction yet operated at a moderate frequency. Therefore, the proposed NoC is divided into two data transfer layers with a single control layer. The data transfer layers are designed using synchronous and asynchronous protocols. The synchronous layer is designated to high-frequency loads, and the asynchronous layer is confined to low-frequency loads. The switching between the layers creates a trade-off between the maximum allowed frequency and the power consumption. The proposed NoC reduces the overall power consumption by 23% when compared with recent previous work. The NoC maintains the same system performance with an 8% area increase over the fully synchronous double-layer in the literature.

Published
2021

4. Long-Range Non-Line of Sight THz Sensing

Author

Thomas Kaiser, Diana Goehringer, Michael Wiemeler, Aman Batra, and Jahangir Alam

Subjects
Physics, Non-line-of-sight propagation, Line-of-sight, Optics, Terahertz radiation, Frequency band, business.industry, Bandwidth (signal processing), Free-space path loss, business, Image resolution, Spectral line, Elektrotechnik
Abstract

Terahertz spectrum is an emerging and promising spectrum as it provides sub-mm spatial resolution and many materials have unique fingerprints at this frequency range. However, the THz spectra suffer from high atmospheric absorption and free space path loss, limiting the propagation range. State-of-the-art THz testbed demonstrations with a bandwidth of >100 GHz are focused on a line of sight (LoS) sensing and limited to a propagation range of sub-2 m. This paper demonstrates non-LoS sensing up to the fifth order of reflection for the frequency band of 220-330 GHz with a range of >6 m.

Published
2021

5. Towards Ubiquitous Low-power Image Processing Platforms

Author

Magnus Jahre, Diana Göhringer, Philippe Millet, Magnus Jahre, Diana Göhringer, and Philippe Millet

Subjects
Electronic circuits, Cooperating objects (Computer systems), Microprocessors, Computer architecture
Abstract

This book summarizes the key scientific outcomes of the Horizon 2020 research project TULIPP: Towards Ubiquitous Low-power Image Processing Platforms. The main focus lies on the development of high-performance, energy-efficient embedded systems for the growing range of increasingly complex image processing applications. The holistic TULIPP approach is described in the book, which addresses hardware platforms, programming tools and embedded operating systems. Several of the results are available as open-source hardware/software for the community. The results are evaluated with several use cases taken from real-world applications in key domains such as Unmanned Aerial Vehicles (UAVs), robotics, space and medicine.Discusses the development of high-performance, energy-efficient embedded systems for the growing range of increasingly complex image processing applications;Covers the hardware architecture of embedded image processing systems, novel methods, toolsand libraries for programming those systems as well as embedded operating systems to manage those systems;Demonstrates results with several challenging applications, such as medical systems, robotics, drones and automotive.

Published
2020

6. SAR signal processing architecture and effects of motion errors for MmWave and THz frequencies

Author

Diana Goehringer, Theo Kreul, Aman Batra, Michael Wiemeler, and Thomas Kaiser

Subjects
Azimuth, Synthetic aperture radar, Signal processing, Motion compensation, Image quality, Computer science, Extremely high frequency, ComputingMethodologies_IMAGEPROCESSINGANDCOMPUTERVISION, Electronic engineering, Image processing, Iterative reconstruction, Elektrotechnik
Abstract

Most commonly used frequencies in Synthetic Aperture Radar (SAR) imaging are from hundreds of MHz to tens of GHz. Nowadays, the unexplored mmWave and THz regimes are being investigated for SAR imaging to have higher resolution. Two research challenges for this technology motion compensation and real-time processing are addressed in this paper. SAR image reconstruction algorithms lack data dependencies. Therefore, it can be processed in a parallel computing environment to accelerate the image reconstruction. This paper presents the theoretical model of a distributed signal processing testbed. The performance enhancement with the inclusion of high performance computing for image processing is also explained. Another challenge for this technology comes from a motion compensation point of view. The SAR signal processing assumption is that the radar-carrying platform follows an ideal path. However, in reality, the platform deviates from this path. Especially at THz, very small deviations in the range of sub-mm produce motion errors because of wavelengths in the range of deviations. It degrades the image quality and provides wrong estimations of range and azimuth scatters. The paper summarizes motion error types, their characterization, and constraint on the amplitude of deviation. Also, the paper presents effects of these errors at 100 GHz with simulation results.

Published
2019

7. Applied Reconfigurable Computing. Architectures, Tools, and Applications : 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings

Author

Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, Pedro C. Diniz, Nikolaos Voros, Michael Huebner, Georgios Keramidas, Diana Goehringer, Christos Antonopoulos, and Pedro C. Diniz

Subjects
Computers, Software engineering, Computer engineering, Computer networks, Computer vision, Artificial intelligence
Abstract

This book constitutes the proceedings of the 14th International Conference on Applied Reconfigurable Computing, ARC 2018, held in Santorini, Greece, in May 2018. The 29 full papers and 22 short presented in this volume were carefully reviewed and selected from 78 submissions. In addition, the volume contains 9 contributions from research projects. The papers were organized in topical sections named: machine learning and neural networks; FPGA-based design and CGRA optimizations; applications and surveys; fault-tolerance, security and communication architectures; reconfigurable and adaptive architectures; design methods and fast prototyping; FPGA-based design and applications; and special session: research projects.

Published
2018

8. Reconfigurable Computing: Architectures, Tools, and Applications : 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings

Author

Diana Goehringer, Marco Domenico Santambrogio, João M.P. Cardoso, Koen Bertels, Diana Goehringer, Marco Domenico Santambrogio, João M.P. Cardoso, and Koen Bertels

Subjects
Computers, Computer engineering, Computer networks, Algorithms
Abstract

This book constitutes the thoroughly refereed conference proceedings of the 10th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2014, held in Vilamoura, Portugal, in April 2014. The 16 revised full papers presented together with 17 short papers and 6 special session papers were carefully reviewed and selected from 57 submissions. The topics covered are applications; methods, frameworks and OS for debug, over-clocking, and relocation; memory architectures; methodologies and tools and architectures.

Published
2014

9. System-Level Design Methodologies for Telecommunication

Author

Nicolas Sklavos, Michael Hübner, Diana Goehringer, Paris Kitsos, Nicolas Sklavos, Michael Hübner, Diana Goehringer, and Paris Kitsos

Subjects
Telecommunication systems--Design and construction, Systems engineering
Abstract

This book provides a comprehensive overview of modern networks design, from specifications and modeling to implementations and test procedures, including the design and implementation of modern networks on chip, in both wireless and mobile applications. Topical coverage includes algorithms and methodologies, telecommunications, hardware (including networks on chip), security and privacy, wireless and mobile networks and a variety of modern applications, such as VoLTE and the internet of things.

Published
2013

10. From Scilab To High Performance Embedded Multicore Systems - The ALMA Approach

Author

Timo Stripf, Michael Huebner, Kostas Masselos, Olivier Sentieys, Diana Goehringer, Daniel Menard, George Goulas, Panayiotis Alefragis, Steven Derrien, Oliver Oey, Nikolaos S. Voros, Kim Sunesen, Gerard Rauwerda, Juergen Becker, Dimitrios Kritharidis, Nikolaos Kavvadias, Nikolaos Mitas, Karlsruhe Institute of Technology (KIT), Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA), Recore Symtems [Enschede], Recore Systems, INTRACOM TELECOM, INTRACOM S.A., Technological Educational Institute of Messolonghi [Messolonghi], Technological Educational Institute of Messolonghi, University of Peloponnese, Fraunhofer Institute of Optronics, System Technologies and Image Exploitation (Fraunhofer IOSB), Fraunhofer (Fraunhofer-Gesellschaft), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), and INTRACOM Telecom

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Multi-core processor, business.industry, Computer science, 020208 electrical & electronic engineering, Process (computing), Multiprocessing, 02 engineering and technology, Integrated circuit design, Toolchain, 020202 computer hardware & architecture, Imperative programming, Computer architecture, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, business, ComputingMilieux_MISCELLANEOUS, Abstraction (linguistics)
Abstract

The mapping process of high performance embedded applications to today's multiprocessor system on chip devices suffers from a complex tool chain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development cost, and shorter time-to-market. Driven by the technology restrictions in chip design, the end of exponential growth of clock speeds, and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies.

Published
2012

11. A Flexible Approach for Compiling Scilab to Reconfigurable Multi-Core Embedded Systems

Author

Timo Stripf, Oliver Oey, Thomas Bruckschloegl, Ralf Koenig, Michael Huebner, Juergen Becker, Gerard Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Menard, Olivier Sentieys, Diana Goehringer, Thomas Perschke, Karlsruhe Institute of Technology (KIT), Technological Educational Institute of Messolonghi [Messolonghi], Technological Educational Institute of Messolonghi, Recore Symtems [Enschede], Recore Systems, Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), University of Peloponnese, Fraunhofer Institute of Optronics, System Technologies and Image Exploitation (Fraunhofer IOSB), Fraunhofer (Fraunhofer-Gesellschaft), INTRACOM Telecom, European Project: 287733,EC:FP7:ICT,FP7-ICT-2011-7,ALMA(2011), CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA), INTRACOM TELECOM, and INTRACOM S.A.

Subjects
Flexibility (engineering), [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Multi-core processor, business.industry, Computer science, Time to market, 020208 electrical & electronic engineering, Multiprocessing, 02 engineering and technology, Toolchain, 020202 computer hardware & architecture, Software, Computer architecture, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, System on a chip, business, ComputingMilieux_MISCELLANEOUS, Abstraction (linguistics)
Abstract

The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides the complexity of the underlying hardware - introduced by software parallelism of multiple cores and the flexibility of reconfigurable architectures - to the end user. The Architecture oriented paraLlelization for high performance embedded Multi-core systems using scilAb (ALMA) European project aims to bridge these hurdles through the introduction and exploitation of a Scilab- and architecture-description-language-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development costs, and shorter time-to-market.

Published
2012

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